2.1.1. Programmed Input/Output Design Example Functional Description - 2026-02-11

F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide
Version
25.3
Figure 4.  Platform Designer System Contents for F-Tile Avalon® -ST IP for PCI Express PIO Design Example [Gen4 x16 variant]The Platform Designer generates this design for up to Gen4 x16 variants.
Figure 5.  Platform Designer System Contents for F-Tile Avalon® -ST IP for PCI Express PIO Design Example [Gen4 x8x8 variant]The Platform Designer generates this design for up to Gen4 x8x8 variants.
Figure 6.  Platform Designer System Contents for F-Tile Avalon® -ST IP for PCI Express PIO Design Example [Gen4 x8 variant]The Platform Designer generates this design for up to Gen4 x8 variants.

This design example includes the following components