| Term | Definition |
|---|---|
|
AVMM |
Avalon Memory Mapped |
|
AVST |
Avalon Streaming |
|
BAM |
Burst Avalon Master |
|
CplD |
Completion with Data |
|
DUT |
Design Under Test |
|
DW |
Double Word |
|
ED |
Example Design |
|
FBE |
First Byte Enable |
|
FIFO |
First In First Out |
|
Gen3 |
PCIe® 3.0 |
|
Gen4 |
PCIe® 4.0 |
|
PIO |
Programmed Input/Output |
|
LBE |
Last Byte Enable |
|
MPS |
Maximum Payload Size |
|
MRd |
Memory Read |
|
MWr |
Memory Write |
|
RX |
Receiver |
|
HIP |
Hard IP |
|
TLP |
Transaction Layer packet |
|
TX |
Transmit |
|
SR-IOV |
Single Root Input/Output Virtualization |