DSP Builder (Advanced Blockset) Handbook - DSP Builder is a high-level synthesis technology that optimizes a high-level, untimed netlist into low-level, pipelined hardware for your target FPGA device and desired clock rate. DSP Builder consists of several Simulink* libraries that allow you to implement DSP designs quickly and easily. DSP Builder implements the hardware as VHDL or Verilog HDL with scripts that integrate with the Quartus Prime software and the RTL simulator. - 2026-01-05
Version
25.3
Answers to Top FAQs
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1.1. DSP Builder for Altera FPGAs Features
1.2. DSP Builder for Altera FPGAs Design Structure
1.3. DSP Builder for Altera FPGAs Libraries
1.4. DSP Builder for Altera FPGAs Device Support
1.5. FPGA Architecture Features for DSP Designs
1.6. DSP Design Flow in FPGAs
1.7. Software and Hardware DSP Design Flows in FPGAs
2. DSP Builder Advanced Blockset Getting Started
2.1. System Requirements - MATLAB Dependencies
2.2. Installing DSP Builder
2.3. Licensing DSP Builder
2.4. Starting DSP Builder in MATLAB on Windows
2.5. Starting DSP Builder in MATLAB on Linux
2.6. Browsing DSP Builder Libraries and Adding Blocks to a New Model
2.7. Browsing and Opening DSP Builder Design Examples
2.8. Creating a New DSP Builder Design with the DSP Builder New Model Wizard
2.8.1. DSP Builder Menu Options
2.8.2. DSP Builder New Model Wizard Setup Script Parameters
2.9. Simulating, Generating, Verifying, and Compiling Your DSP Builder Design
2.10. Generating a Fast Simulation Model
3. DSP Builder Design Flow
3.1. Implementing your Design in DSP Builder Advanced Blockset
3.1.1. Dividing your DSP Builder Design into Subsystems
3.1.2. Connecting DSP Builder Subsystems
3.1.2.1. DSP Builder Block Interface Signals
3.1.2.1.1. Multichannel Systems with IP Library Blocks
3.1.2.1.2. Valid, Channel, and Data Examples
3.1.2.2. Periods
3.1.2.3. Sample Rate
3.1.2.4. Building Multichannel Systems
3.1.2.4.1. Multichannel Systems with IP Library Blocks
3.1.2.5. Channelization for Two Channels with a Folding Factor of 3
3.1.2.6. Channelization for Four Channels with a Folding Factor of 3
3.1.2.7. Synchronization and Scheduling of Data with the Channel Signal
3.1.2.8. Simulink vs Hardware Design Representations
3.1.3. Creating a New Design by Copying a DSP Builder Design Example
3.1.3.1. Creating a New Design From the DSP Builder FIR Design Example and Changing the Namespaces
3.1.4. Vectorized Inputs
3.2. Verifying your DSP Builder Advanced Blockset Design in Simulink and MATLAB
3.2.1. Verifying your DSP Builder Advanced Blockset Design with a Testbench
3.2.1.1. Visualization Features
3.2.2. Running DSP Builder Advanced Blockset Automatic Testbenches
3.2.2.1. dspba.runModelsimATB
3.2.2.2. Running All Automatic Testbenches
3.2.2.3. The command run_all_atbs Command Syntax
3.2.2.4. Testbench Error Messages
3.2.3. Using DSP Builder Advanced Blockset References
3.2.4. Setting Up Stimulus in DSP Builder Advanced Blockset
3.2.5. Analyzing your DSP Builder Advanced Blockset Design
3.3. Exploring DSP Builder Advanced Blockset Design Tradeoffs
3.3.1. Bit Growth
3.3.2. Managing Bit Growth in DSP Builder Advanced Blockset Designs
3.3.3. Using Rounding and Saturation in DSP Builder Advanced Blockset Designs
3.3.4. Scaling with Primitive Blocks
3.3.5. Changing Data Type with Convert Blocks and Specifying Output Types
3.3.5.1. The Convert Block and Real-world Values
3.3.5.2. Output Data Types on Primitive Blocks
3.4. Verifying your DSP Builder Design with C++ Software Models
3.4.1. Software Model Options
3.4.2. Software Model Generated Files
3.4.3. Software Model Compilers
3.4.4. Compiling and Running Software Model Testbenches
3.4.5. Testing the Software Model
3.4.5.1. Linking to External Libraries
3.4.6. MATLAB MEX Function Wrapper for a Generated Software Model
3.4.6.1. Driving the Model
3.4.6.2. MEX Model Code
3.4.6.3. Complete the MEX Function
3.4.6.4. Compile, Run, and Test the MEX Function
3.5. Verifying your DSP Builder Advanced Blockset Design in the ModelSim Simulator
3.5.1. Automatic Testbench
3.5.1.1. DSP Builder Advanced Blockset Automatic Testbench Files
3.5.2. DSP Builder Advanced Blockset ModelSim Simulations
3.6. Verifying Your DSP Builder Design in Hardware
3.6.1. Hardware Verification
3.6.1.1. Real-Time Hardware Verification Design Example
3.6.1.1.1. Running the Real-Time Hardware Verification Design Example
3.7. Integrating Your DSP Builder Advanced Blockset Design into Hardware
3.7.1. DSP Builder Generated Files
3.7.2. DSP Builder Designs and the Quartus Prime Project
3.7.2.1. Adding a DSP Builder Advanced Blockset Design to an Existing Quartus Prime Project
3.7.3. Interfaces with a Processor Bus
3.7.3.1. Assigning Base Addresses in DSP Builder Designs
3.7.3.2. Updating Registers with the Nios II Processor
3.7.4. DSP Builder Designs in Platform Designer
3.7.4.1. Integrating a DSP Builder Design to a Platform Designer System
3.7.4.2. Modifying Avalon Streaming Blocks
3.7.4.3. Restrictions for DSP Builder Designs with Avalon Streaming Interface and AXI4-Stream Blocks
3.7.4.4. Connecting Conduit Interfaces
4. Primitive Library Blocks Tutorial
4.1. Creating a Fibonacci Design from the DSP Builder Primitive Library
4.2. Setting the Parameters on the Testbench Source Blocks
4.3. Simulating the Fibonacci Design in Simulink
4.4. Modifying the DSP Builder Fibonacci Design to Generate Vector Signals
4.5. Simulating the RTL of the Fibonacci Design
5. IP Tutorial
5.1. Creating an IP Design
5.2. Simulating the IP Design in Simulink
5.3. Viewing Timing Closure and Viewing Resource Utilization for the DSP Builder IP Design
5.4. Reparameterizing the DSP Builder FIR Filter to Double the Number of Channels
5.5. Doubling the Target Clock Rate for a DSP Builder IP Design
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6.1. DSP Builder Design Configuration Block Design Examples
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6.2. DSP Builder FFT Design Examples
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6.2.26. Variable-Size Supersampled FFT with Bit-Reverse
6.3. DSP Builder DDC Design Example
6.3.1. DDC Design Example Subsystem
6.3.2. Building the DDC Design Example
6.3.2.1. DDC Design Example Generated Files
6.4. DSP Builder Filter Design Examples
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6.4.9. IIR: Full-rate Fixed-point
6.4.10. IIR: Full-rate Floating-point
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6.5. DSP Builder Finite State Machine Design Example
6.6. DSP Builder Folding Design Examples
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Position, Speed, and Current Control for AC Motors (with ALU Folding)
6.6.3. About FOC
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6.9. DSP Builder HDL Import Design Example
6.9.1. Performing a Cosimulation
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6.11. DSP Builder Fixed-Point Matrix Multiply Engine Design Example
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6.14.20. QRD Solver
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6.14.27. Transmit and Receive Modem
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7. DSP Builder Design Rules, Design Recommendations, and Troubleshooting
7.1. DSP Builder Design Rules and Recommendations
7.2. Troubleshooting DSP Builder Designs
7.2.1. About Loops
7.2.2. Closing Timed feedback Loops
7.2.3. Loops, Clock Cycles, and Data Cycles
8. About DSP Builder Optimization
8.1. Associating DSP Builder with MATLAB
8.2. Setting Up Simulink for DSP Builder Designs
8.2.1. Setting Up Simulink Solver
8.2.2. Setting Up Simulink Signal Display Option
8.3. The DSP Builder Windows Shortcut
8.4. Setting DSP Builder Design Parameters with MATLAB Scripts
8.4.1. Running Setup Scripts Automatically
8.4.2. Defining Unique DSP Builder Design Parameters
8.4.3. Example DSP Builder Custom Scripts
8.5. Managing your Designs
8.5.1. Managing Basic Parameters
8.5.2. Creating User Libraries and Converting a Primitive Subsystem into a Custom Block
8.5.3. Revision Control
8.6. How to Manage Latency
8.6.1. Reading the Added Latency Value for an IP Block
8.6.2. Zero Latency Example
8.6.3. Implicit Delays in DSP Builder Designs
8.6.4. Distributed Delays in DSP Builder Designs
8.6.5. Latency and fMAX Constraint Conflicts in DSP Builder Designs
8.6.6. Control Units Delays
8.7. Flow Control in DSP Builder Designs
8.8. Reset Minimization
8.9. About Importing HDL
9. About Folding
9.1. ALU Folding
9.1.1. ALU Folding Limitations
9.1.2. ALU Folding Parameters
9.1.3. ALU Folding Simulation Rate
9.1.4. Using ALU Folding
9.1.5. Using Automated Verification
9.1.6. Ready Signal
9.1.7. Connecting the ALU Folding Ready Signal
9.1.8. About the ALU Folding Start of Packet Signal
9.2. Removing Resource Sharing Folding
10. Floating-Point Data Types
10.1. DSP Builder Floating-Point Data Type Features
10.2. DSP Builder Supported Floating-Point Data Types
10.3. DSP Builder Round-Off Errors
10.4. Trading Off Logic Utilization and Accuracy in DSP Builder Designs
10.5. Upgrading Pre v14.0 Designs
10.6. Floating-Point Sine Wave Generator Tutorial
10.6.1. Creating a Sine Wave Generator in DSP Builder
10.6.2. Using Data Type Variables to Parameterize Designs
10.6.3. Using Data-Type Propagation in DSP Builder Designs
10.6.4. DSP Builder Testbench Verification
10.6.4.1. Tuning ATB Thresholds
10.6.4.2. Writing Application Specific Verification
10.6.4.3. Bit-Accurate Simulation
10.6.4.4. Adder Trees and Scalar Products
10.6.4.5. Creating Floating-Point Accumulators for Designs that Use Iteration
10.7. Newton-Raphson Root Finding Tutorial
10.7.1. Implementing the Newton Design
10.7.2. Improving DSP Builder Floating-Point Designs
10.8. Forcing Soft Floating-point Data Types with the Advanced Options
11. Design Configuration Library
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11.2.1. DSP Builder Memory and Multiplier Trade-Off Options
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12. IP Library
12.1. Channel Filter and Waveform Library
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12.1.1.1. Common CIC and FIR Filter Features
12.1.1.2. Updated Help
12.1.1.3. Half-Band and L-Band Nyquist FIR Filters
12.1.1.4. Parameterization of CIC and FIR Filters
12.1.1.5. Setting and Changing FIR Filter Coefficients at Runtime in DSP Builder
12.1.2. DSP Builder FIR Filters
12.1.2.1. FIR Filter Avalon-MM Interfaces
12.1.2.2. Reconfigurable FIR Filters
12.1.2.3. FIR Filter Coefficient Sharing
12.1.2.4. FIR Filter Reset
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Decimating FIR
Fractional Rate FIR
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Interpolating FIR
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12.1.10.1. NCO Block Phase Increment and Inversion
12.1.10.2. NCO Block Phase Increment Memory Registers
12.1.10.3. NCO Block Frequency Hopping
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Single-Rate FIR
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12.2.1. Dependent Latency Expressions
12.3. FFT IP Library
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12.4. Machine Learning Library
12.4.1. Machine Learning example designs
12.4.1.1. Image Classification
12.4.1.2. Digital Predistortion
12.4.1.3. Channel Estimation
13. Interfaces Library
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13.2. Streaming Library
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13.2.4. AXI4-Stream Blocks (AXI4StreamReceiver and AXI4StreamTransmitter)
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14.1. Vector and Complex Type Support
14.1.1. Vector Type Support
14.1.1.1. Element by Element Mode
14.1.1.2. Mathematical Vector Mode
14.1.1.3. Interactions with Simulink
14.1.2. Complex Support
14.1.2.1. Interactions with Simulink
14.2. DFT Design Elements Library
14.2.1. DFT (DFT)
14.2.2. Reorder (ReorderBlock)
14.2.3. Reorder and Rescale (ReorderAndRescale)
14.3. FFT Design Elements Library
14.3.1. About Pruning and Twiddle for FFT Blocks
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14.3.16. Multiwire Variable Bit Reverse (MultiwireVariableBitReverse)
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14.4. Primitive Basic Blocks Library
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14.5. Primitive Configuration Library
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14.5.5.1. Scheduled Synthesis
14.5.5.2. Updated Help
14.6. Primitive Design Elements Library
Anchored Delay
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14.6.6.1. Adding a Finite State Machine Block to your DSP Builder Design
14.6.6.2. Modifying the Finite State Machine Block Specification File
14.6.6.3. Implement Token Passing with the Finite State Machine
14.6.6.4. Implementing a One Shot Counter with the Finite State Machine
14.6.6.5. Specifying ForLoop Control Units
14.6.6.6. Creating the Finite State Machine Configuration File
14.6.6.7. Upgrading Finite State Machine Blocks from v23.2 and Earlier
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15. Utilities Library
15.1. Analyze and Test Library
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15.1.2. Dechannelizer
15.1.3. Channelizer
15.1.4. Display Resources
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15.2. HDL Import Library
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15.3. Beta Blocks Library
15.3.1. SYCL
15.3.1.1. Implementing a SYCL Block
16. Simulink Supported Blocks
17. DSP Builder (Advanced Blockset) Handbook
18. Document Revision History for DSP Builder (Advanced Blockset) Handbook