2.2. Simulating the Testbench - Altera provides a fixed testbench as an example to simulate the SDI Audio Altera FPGA IP cores. Use this testbench to simulate the SDI Audio Embed and the associated SDI Audio Extract IP cores, and the SDI Clocked Audio Input and the associated SDI Clocked Audio Output IP cores. - 2025-12-16

SDI Audio IP User Guide
Version
25.3
Altera provides a fixed testbench as an example to simulate the SDI Audio Altera FPGA IP cores. Use this testbench to simulate the SDI Audio Embed and the associated SDI Audio Extract IP cores, and the SDI Clocked Audio Input and the associated SDI Clocked Audio Output IP cores.

You can obtain the testbench from ip/altera/audio_ip/simulation directory.

To use the testbench with the ModelSim simulator, follow these steps:

The following table lists the SDI Audio IP cores to generate with recommended parameter configurations and file names.

Table 3.  SDI Audio IP Cores to Generate
IP Name Number of Supported Audio Groups Parameter Include Avalon-ST Interface Parameter Include Avalon-MM Control Interface Parameter IP Variant File Name
Audio Embed 4 Off On audio_embed_top.ip
Audio Embed 4 On On audio_embed_avalon_top.ip
Audio Extract — Off On audio_extract_top.ip
Audio Extract — On On audio_extract_avalon_top.ip
Clocked Audio Input — — On clocked_audio_input_top.ip
Clocked Audio Output — — On clocked_audio_output_top.ip
  1. Open the Quartus® Prime software.
  2. On the File menu, click the New Project Wizard.
  3. Specify a sensible name for the project working directory, project name, and project top-level entity, and click Next.
  4. Select Empty Project and click Next.
  5. On the Add Files menu, leave everything empty and click Next.
  6. Select the device family (for example, Arria 10 (GX/SX/GT)) and the desired FPGA device (for example, 10AS066N3F40E2SG).
  7. Click Finish.
  8. Outside the Quartus® Prime software, copy the simulation folder including all simulation testbench files contained within this folder (for example, from /tools/acds/19.2/57/linux64/ip/altera/audio_ip/simulation) to your project working directory.
  9. In the IP Catalog (Tools > IP Catalog), locate and double-click the IP under Library > Interface Protocols > Audio & Video > <IP Name e.g. Audio Embed> .
    The New IP Variant prompt appears.
  10. Save the IP variant according to the file name in the SDI Audio IP Cores to Generate table.
    The IP Parameter Editor appears.
  11. Configure the IP according to the SDI Audio IP Cores to Generate table while leaving the rest of the parameters at default.
  12. Click Generate HDL.
  13. On the Generation menu, select Create Simulation Model > Verilog and click Generate.
  14. Close the IP Parameter Editor after IP generation is complete.
  15. Repeat steps 9 to 14 for all IPs listed in the SDI Audio IP Cores to Generate table.
  16. Set the QUARTUS_ROOTDIR environment variable to point to your installation of the Quartus® Prime software though the Windows command prompt or Linux terminal.
    Command line examples:

    windows64> setx QUARTUS_ROOTDIR “C:\intelFPGA_pro\19.2\quartus”

    linux-bash> export QUARTUS_ROOTDIR=“/tools/acds/19.2/57/linux64/quartus”

    linux-csh> setenv QUARTUS_ROOTDIR “/tools/acds/19.2/57/linux64/quartus”

  17. Start the ModelSim simulator.
  18. Run run.tcl in your project working directory simulation folder. This file compiles the design.
    A selection of signals appears on the waveform viewer. The simulation runs automatically, providing a pass or fail indication upon completion.

Guidelines

When you use the testbench to simulate the IP cores, consider the following guidelines:

  • Select the video standard for the video test source through the generic G_TEST_STD of the testbench entity. Set 0, 1, 2, or 3 to select SD-SDI, HD-SDI, 3G-SDI Level A, or 3G-SDI Level B.
  • The audio test source uses the 48 kHz clock output from the SDI Audio Embed IP core. The audio test sample comprises an increasing count which allows the testbench to check the extracted audio at the far end of the processing chain.
  • The SDI Audio Embed IP core accepts these video and audio test sources to create a video stream with embedded audio. The SDI Audio Extract IP core then receives the resulting stream to recover the embedded audio. Examine this audio sequence to ensure that the count pattern that was created is preserved.
  • The synchronization requirements of the receive FIFO buffer in the SDI Audio Extract IP core allows you to repeat the occasional sample from the SDI Audio Extract IP core. Synchronization may take up to a field period of typically 16.7 ms to complete.
  • Select G_INCLUDE_AVALON_ST = 1, if you want to instantiate another SDI Audio Embed IP core with Avalon streaming interface (with embedded clocked audio output component) and the associated SDI Audio Extract IP core with Avalon streaming interface (with embedded clocked audio input component) in this testbench.