5.3. SDI Audio Clocked Input Signals - 2025-12-16

SDI Audio IP User Guide

Version: 25.3

The following tables list the signals for the SDI Audio Clocked Input IP cores.

Table 20. SDI Audio Clocked Input Input and Output Signals
Signal	Width	Direction	Description
`aes_clk`	[0:0]	Input	Audio input clock.
`aes_de`	[0:0]	Input	Audio data enable.
`aes_ws`	[0:0]	Input	Audio word select.
`aes_data`	[0:0]	Input	Audio data input in internal AES format.

Table 21. SDI Audio Clocked Input Avalon Streaming Interface Audio SignalsThis table lists the Avalon-ST audio signals when you instantiate the SDI Audio Clocked Input IP core in Platform Designer (Standard).
Signal	Width	Direction	Description
`aud_clk`	[0:0]	Input	Clocked audio clock. All the audio input signals are synchronous to this clock.
`aud_ready`	[0:0]	Input	Avalon streaming interface ready signal. Assert this signal when the device is able to receive data.
`aud_valid`	[0:0]	Output	Avalon streaming interface valid signal. The core asserts this signal when it produces data.
`aud_sop`	[0:0]	Output	Avalon streaming interface start of packet signal. The core asserts this signal when it is starting a new frame.
`aud_eop`	[0:0]	Output	Avalon streaming interface end of packet signal. The core asserts this signal when it is ending a frame.
`aud_data`	[23:0]	Output	Avalon streaming interface data bus. The core asserts this signal to transfer data.

Table 22. SDI Audio Clocked Input Direct Control Interface SignalsThe direct control interface is internal to the audio extract component.
Signal	Width	Direction	Description
`channel0`	[7:0]	Input	Indicates the channel number of audio channel 1.
`channel1`	[7:0]	Input	Indicates the channel number of audio channel 2.
`fifo_status`	[7:0]	Input	Drive bit 7 high to reset the clocked audio input FIFO buffer.
`fifo_reset`	[0:0]	Output	Assert this signal when the clocked audio input FIFO buffer overflows.