Arria 10 Device Overview - Provides an overview of the Arria 10 device family features, ordering codes options, maximum resource counts, and available device packages. - 2025-06-04

Arria 10 Device Overview
Key Advantages of Arria 10 Devices
Summary of Arria 10 Features
Arria 10 Device Variants and Packages
Arria 10 GX
Available Options
Maximum Resources
Package Plan
Arria 10 GT
Available Options
Maximum Resources
Package Plan
Arria 10 SX
Available Options
Maximum Resources
Package Plan
I/O Vertical Migration for Arria 10 Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Types of Embedded Memory
Embedded Memory Capacity in Arria 10 Devices
Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources
Clock Networks
Fractional Synthesis and I/O PLLs
Fractional Synthesis PLLs
I/O PLLs
FPGA General Purpose I/O
External Memory Interface
Memory Standards Supported by Arria 10 Devices
PCIe Gen1, Gen2, and Gen3 Hard IP
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Interlaken Support
10 Gbps Ethernet Support
Low Power Serial Transceivers
Transceiver Channels
PMA Features
PCS Features
PCS Protocol Support
SoC with Hard Processor System
Key Advantages of 20-nm HPS
Features of the HPS
System Peripherals and Debug Access Port
HPS–FPGA AXI Bridges
HPS SDRAM Controller Subsystem
FPGA Configuration and HPS Booting
Hardware and Software Development
Dynamic and Partial Reconfiguration
Dynamic Reconfiguration
Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
SEU Error Detection and Correction
Power Management
Incremental Compilation
Document Revision History for Arria 10 Device Overview

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