Arria 10 GX/GT Device Errata and Design Recommendations - This document contains the descriptions, workarounds and status of the errata for Arria 10 GX/GT devices. - 2026-04-21

1. About this Document
2. Design Recommendations for Arria 10 GX/GT Devices
2.1. Arria 10 Device Lifetime Guidance
2.1.1. Design Recommendation
3. Device Errata for Arria 10 GX/GT Devices
3.1. Automatic Lane Polarity Inversion for PCIe Hard IP
3.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software
3.3. High VCCBAT Current when VCC is Powered Down
3.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR)
3.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
4. Document Revision History for Arria 10 GX/GT Device Errata and Design Recommendations

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