Serial Lite III Streaming IP User Guide - This IP provides features for high bandwidth streaming data in chip-to-chip, board-to-board, and backplane applications. - 2025-11-04
Version
24.1
1. Serial Lite III Streaming IP Quick Reference
2. About the Serial Lite III Streaming IP
2.1. Serial Lite III Streaming IP Protocol
2.2. Serial Lite III Streaming IP Protocol Operating Modes
2.2.1. Continuous Mode
2.2.2. Burst Mode
2.3. Performance and Resource Utilization
3. Getting Started
3.1. Installing and Licensing IPs
3.2. IP Evaluation Mode
3.2.1. Altera FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options
3.3.1. Serial Lite III Streaming IP Parameter Editor
3.3.2. Arria 10 and Cyclone 10 GX Designs
3.4. Serial Lite III Streaming IP Parameters
3.4.1. Parameters
3.4.2. Parameter Settings for Stratix 10 Devices
3.4.3. Parameter Settings for Arria 10 and Cyclone 10 GX Devices
3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.5. Transceiver Reconfiguration Controller for Stratix V and Arria V GZ Designs
3.6. IP Generation Output ( Quartus Prime Pro Edition)
3.7. IP Core Generation Output ( Quartus Prime Standard Edition)
3.8. Simulating
3.8.1. Simulating IP Cores
3.8.2. Simulation Parameters
3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples
4.1. Serial Lite III Streaming IP Core Design Example for Stratix 10 Devices
4.2. Serial Lite III Streaming IP Core Design Example for Arria 10 and Cyclone 10 GX Devices
4.3. Serial Lite III Streaming IP Design Examples for Stratix V Devices
5. Serial Lite III Streaming IP Functional Description
5.1. IP Architecture
5.1.1. Serial Lite III Streaming Source Core
5.1.1.1. Source Application Module
5.1.1.2. Source Adaptation Module
5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode
5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core
5.1.2.1. Sink Application Module
5.1.2.2. Sink Adaptation Module
5.1.2.3. Lane Alignment Module
5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode
5.1.2.5. Sink Clock Generator
5.1.3. Serial Lite III Streaming IP Core Duplex Core
5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode
5.1.5. Stratix 10, Arria 10, Cyclone 10 GX, Stratix V, and Arria V GZ Variations
5.2. Transmission Overheads and Lane Rate Calculations
5.3. Reset
5.4. Link-Up Sequence
5.5. Error Detection, Reporting, and Recovering Mechanism
5.6. CRC-32 Error Injection
5.7. FIFO ECC Protection
5.8. User Data Interface Waveforms
5.9. Signals
5.9.1. Serial Lite III Streaming IP Interface Signals
5.9.2. Signals for Stratix 10 Devices
5.9.3. Signals for Arria 10 and Cyclone 10 GX Devices
5.9.4. Signals for Stratix V and Arria V GZ Devices
5.10. Accessing Configuration and Status Registers
6. Serial Lite III Streaming IP Clocking Guidelines
6.1. Standard Clocking Mode
6.1.1. Standard Clocking Mode in Serial Lite III Streaming IP Core ( Stratix 10 Devices)
6.1.2. Standard Clocking Mode in Arria 10, Cyclone 10 GX, Stratix V, and Arria V Devices
6.2. Advanced Clocking Mode
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix 10 Devices)
6.2.2. Advanced Clocking Mode Structure For Arria 10, Cyclone 10 GX, Stratix V, and Arria V Devices
6.3. Standard Clocking Mode vs Advanced Clocking Mode
6.4. Clocking Implementation Guidelines
6.4.1. Choosing TX PLL Type
6.5. Core Latency
7. Serial Lite III Streaming IP Configuration and Status Registers
7.1. Register Map
7.2. Configuration and Status Registers
8. Serial Lite III Streaming IP Debugging Guidelines
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
8.2. Serial Lite III Streaming IP Link Debugging
8.2.1. Source Core Link Debugging
8.2.2. Sink Core Link Debugging
9. Serial Lite III Streaming IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming IP User Guide