| Signal Role | Width | Direction | Description |
|---|---|---|---|
| clk | 1 | Input | Input clock to clock the Mailbox Client IP. The maximum frequency is 250 MHz. |
| reset | 1 | Input | Reset that resets the Mailbox Client
IP. To reset the IP, assert the reset signal high for at least 2 clk cycles. To ensure the Mailbox Client IP functions correctly when the device enters user mode, your design must include the Reset Release
IP to hold the reset until the FPGA fabric entered user mode. Altera recommends using a reset synchronizer when connecting the user reset or output of the Reset Release
IP to the reset port of the Mailbox Client
IP. To implement the reset synchronizer, use the Reset Bridge IP available in the Platform Designer.
Note: For IP instantiation and connection guidelines in the Platform Designer, refer to the Required Communication and Host Components for the Remote System Update Design Example figure in the
Stratix® 10 Configuration User Guide.
Note: For IP instantiation guidelines, refer to the respective device's Configuration User Guide.
|
| irq | 1 | Output | Interrupt signal. Drives the value of the AND of the interrupt status and interrupt enable registers. |