5. Document Revision History for the F-Tile Serial Lite IV IP Design Example User Guide - 2025-12-30

F-Tile Serial Lite IV IP Design Example User Guide
Version
25.3.1
Document Version Quartus® Prime Version IP Version Changes
2026.01.05 25.3.1 9.8.0
  • Updated sections:
    • Hardware and Software Requirements
    • Features
    • Analog Parameters
  • Updated Table: Parameters in the Example Design Tab.
2025.08.14 25.1.1 9.7.0
  • Updated Hardware and Software Requirements section.
  • Updated Figure: FGT PMA Settings.
2025.05.09 25.1 9.6.0
  • Updated Hardware and Software Requirements section.
  • Updated Deterministic Latency section.
  • Updated Figure: F-Tile Serial Lite IV DL Example Design Diagram.
  • Removed sections:
    • TX DL Shim Wrapper
    • RX DL Shim Wrapper
    • Deterministic Latency Design Considerations
2025.01.24 24.3 9.5.0
  • Updated Hardware and Software Requirements section.
  • Updated Example Design Tab figure.
  • Updated Parameters in the Example Design Tab table.
  • Updated Deterministic Latency Design Considerations section.
  • Updated Recommended Deterministic Latency RBD values table.
2024.07.06 24.1 9.3.0
  • Updated Clock Pin Output for FGT Designs table.
  • Updated RX DL Shim Wrapper section.
  • Updated Analog Parameters section.
2024.04.01 24.1 9.3.0
  • Updated Hardware and Software Requirements section.
  • Updated the following tables:
    • Clock Pin Output for FGT Designs
    • Error Condition Behavior
  • Added the following sections:
    • Deterministic Latency
    • SYSREF Pulse Generator
    • TX DL Shim Wrapper
    • RX DL Shim Wrapper
    • Deterministic Latency Design Considerations
2023.10.02 23.3 9.1.0
  • Updated the product family name to "Intel Agilex 7."
  • Added information about Device Speed Grade Support.
  • Added Riviera-PRO™ simulator in Table: Testbench Simulation Scripts and in Hardware and Software Requirements section.
  • Added Analog Parameters section.
  • Added reg_write <avmm2_address> <desired_value>, reg_read <avmm2_address>, proc_avmm1_write <avmm1_address> <desired_value> and proc_avmm1_read <avmm1_address> commands in Table: System Console Commands for Hardware Testing.
  • Added information for Riviera-PRO™ simulator and updated file directories in Compiling and Simulating the Design section.
  • Updated the following figures:
    • Example Design Tab
    • Directory Structure for Agilex™ 7 F-Tile Serial Lite IV Design Example
    • Example of Hardware Design Example Test Result in System Console
    • MAC and PCS Tab
2022.10.14 22.3 7.0.0
  • Updated Table: Design Example Components.
    • Updated description for the F-Tile Serial Lite IV Intel FPGA IP component.
  • Updated Hardware and Software Requirements.
  • Updated Table: Parameters in the Example Design Tab.
    • Updated description for the Select Board parameter.
  • Updated Directory Structure to add new folder.
  • Updated Figure: Directory Structure for Intel Agilex F-Tile Serial Lite IV Design Example.
    • Added new folder, ed_hwtest.
    • Updated folders, ed_sim and ed_synth.
  • Updated the steps in Compiling and Testing the Design.
  • Updated the transceiver data rates in Features.
  • Updated Table: System Console Commands for Hardware Testing.
  • Added Figure: Steps to perform Hardware Testing.
  • Updated the steps in Setting Up and Running the Toolkit.
  • Updated Figure: Setting JTAG Master.
  • Updated Toolkit GUI Setting.
    • Corrected PHY to PCS.
    • Updated steps.
  • Updated Figure: MAC and PCS Tab.
  • Updated Figure: Traffic Statistics Tab.
  • Updated F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide Archives.
2021.12.13 21.4 3.0.0
  • Added a footnote to the supported transceiver data rates in Features.
  • Added a new topic—Hardware Testing.
  • Updated topic title Software Requirements to Hardware and Software Requirements and added hardware testing.
  • Updated Figure: Example Design Tab.
  • Updated the steps in Compiling and Testing the Design.
  • Updated the command for ModelSim® and QuestaSim® simulators in Table: Testbench Simulation Scripts.
  • Updated Table: Parameters in the Example Design Tab to include the Agilex I-Series Transceiver-SoC Development Kit option under the Select Board parameter.
2021.10.22 21.3 3.0.0
  • Updated Software Requirements.
  • Corrected the steps in Compiling and Simulating the Design.
  • Updated Table: Testbench Simulation Scripts to include information for VCS® MX and QuestaSim® simulators.
2021.08.18 21.2 2.0.0 Initial release.