When the Deterministic Latency (DL) option is selected in the F-Tile Serial Lite IV
IP, the following main components supporting the DL solution will be included in the design example:
- SYSREF Pulse Generator
- Deterministic Latency Top Wrapper
Note: Deterministic Latency value = latency between TX DL SHIM input (from USR_IF) and RX DL SHIM output (to USR_IF).
Figure 22.
F-Tile Serial Lite IV DL Example Design Diagram