| Parameter | Description |
|---|---|
| Generate Files for |
The IP generates the necessary design example files for simulation and compilation. Simulation—select this option to generate the necessary design simulation files. Synthesis—select this option to generate the necessary design synthesis files. Use these files to compile the design in the Quartus® Prime Pro Edition software for hardware testing. |
| Generate File Format | The format of the RTL files for simulation—Verilog or VHDL. |
| Select Board | Supported hardware for design implementation. When you select an Altera FPGA development
board, the Target Device is
the one that matches the device on the Development Kit. If this menu is grayed out, there is no supported board for the options that you select. Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile): This option allows you to test the design example on the selected Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 1 4x F-Tile). Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 2 4x F-Tile): This option allows you to test the design example on the selected Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (Production 2 4x F-Tile). Note: This option is only available when your target
device is:
No Development Kit: This option excludes the hardware aspects for the design example. |
| Device Initialization Clock |
Select the device initialization clock for the Example Design. The development kit supports only OSC_CLK_1_125MHZ by default. If you are using a different development kit board, please refer to the specifications of the board and set the recommended clock. |
| Change Target Device | Select a different device grade for IP development kit. For device-specific details, refer to the device datasheet on the Altera FPGA website. |
The F-Tile Serial Lite IV
IP parameter editor includes an
Example Design tab for you to specify parameters before
generating the design example.
Figure 4. Example Design Tab
