2.4. Compiling and Simulating the Design - The design example testbench simulates your generated design. - 2025-12-30

F-Tile Serial Lite IV IP Design Example User Guide
Version
25.3.1
The design example testbench simulates your generated design.
  1. Change the working directory to <example_design_directory>/ed_sim.
  2. Run the simulation script for the simulator of your choice.
    Table 6.  Testbench Simulation Scripts
    Simulator File Directory Command
    ModelSim® <variation name>sl4_f_0_example_design/ed_sim source run_mentor.tcl
    Note: source evaluates a file or resource as a Tcl script (Tools - Tcl - Execute - Macro).
    QuestaSim®
    VCS® <variation name>sl4_f_0_example_design/ed_sim sh run_vcs.sh
    VCS® MX <variation name>sl4_f_0_example_design/ed_sim sh run_vcsmx.sh
    Xcelium™ <variation name>sl4_f_0_example_design/ed_sim sh run_xcelium.sh
    Riviera-PRO™ <variation name>sl4_f_0_example_design/ed_sim riviera -do run_riviera.do
  3. When the simulation is complete, you can now analyze the results and verify the design. A successful simulation ends with the following message, "Test Passed."
#    ****************************** Data Forwarding Test Completed ****************************
#    
#    ************************************** Test Completed ************************************
#    
#    End time                       = 534579600
#    
#    Total words tranferred         = 10000
#    
#    Number of bursts               = 0
#    
#    Random number generator seed   = 1756255697
#    
#    Link Latency                   = 434 ns
#    
#    *************************************** Test Passed **************************************