1.7. Testing the Hardware Design Example - 2025-12-16

F-Tile CPRI PHY IP Design Example User Guide
Version
25.1
After you compile the F-Tile CPRI PHY Altera® FPGA IP core design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP core and its PHY IP core registers.

To start the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Agilex™ 7 device, in the Quartus® Prime Pro Edition software, click Tools > System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest_sl.
  3. Type source main_script.tcl to open a connection to the JTAG master and start the test.