The JTAG to Avalon Host Bridge Altera FPGA IP sends and receives commands from system console to example design’s Avalon® memory-mapped interface (host of Avalon memory-mapped decoder) via JTAG. In simulation, this block is bypassed, and replaced with a Verilog force statement. The Avalon® memory-mapped interface read and write task simulates the system console operation. For more information, refer to SPI Agent/JTAG to Avalon Host Bridge Cores.