The IOPLL Intel FPGA IP generates a 250 MHz clock from a 100 MHz reference clock. The 250 MHz clock is the sampling clock (sampling_clk) for the deterministic latency measurement. For more information, refer to IOPLL Intel FPGA IP Core.
The IOPLL Intel FPGA IP generates a 250 MHz clock from a 100 MHz reference clock. The 250 MHz clock is the sampling clock (sampling_clk) for the deterministic latency measurement. For more information, refer to IOPLL Intel FPGA IP Core.