The design example demonstrates the basic functionality of the F-Tile CPRI PHY Altera® FPGA IP core. You can generate the design from the Example Design tab in the F-Tile CPRI PHY Altera® FPGA IP parameter editor.
To generate the design example, you must first set the parameter values for
the IP core variation you intend to generate in your end product. You can choose to generate
the design example with or without the RS-FEC feature. The RS-FEC feature is available with
10.1376,
12.1651,
and 24.33024 Gbps CPRI line bit rates.
| CPRI Line Bit Rate (Gbps) | RS-FEC Support | Reference Clock (MHz) | Deterministic Latency Support |
|---|---|---|---|
| 1.2288 | No | 153.6 or 122.88 | Yes |
| 2.4576 | No | 153.6 or 122.88 | Yes |
| 3.072 | No | 153.6 or 122.88 | Yes |
| 4.9152 | No | 153.6 or 122.88 | Yes |
| 6.144 | No | 153.6 or 122.88 | Yes |
| 9.8304 | No | 153.6 or 122.88 | Yes |
| 10.1376 | With and Without | 184.32 or 122.88 | Yes |
| 12.1651 | With and Without | 184.32 or 122.88 | Yes |
| 24.33024 | With and Without | 184.32 or 122.88 | Yes |