F-Tile CPRI PHY IP Design Example User Guide - This document describes the F-Tile CPRI PHY IP design example generation, simulation, compilation, and testing. - 2025-03-30

Version: 25.1

1. Quick Start Guide
1.1. Hardware and Software Requirements
1.2. Generating the Design Example
1.2.1. Design Example Parameters
1.2.2. Analog Parameters for F-Tile IPs
1.3. Directory Structure
1.4. Simulating the Design Example
1.4.1. Simulating the Design Example Testbench
1.4.2. Simulating the Design Example Testbench Simplified Model
1.5. Compiling the Compilation-Only Project
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Hardware Design Example
1.8. Transceiver Toolkit
2. Design Example Description
2.1. Features
2.2. Design Example Components
2.2.1. Packet Client
2.2.2. Round Trip Counter
2.2.3. Sources and Probes
2.2.4. Avalon Memory-Mapped Decoder
2.2.5. JTAG Host
2.2.6. IOPLL
2.2.7. System PLL
2.3. Simulation Design Example
2.4. F-Tile CPRI IP Hardware Design Example
2.5. Interface Signals
2.6. Design Example Registers
3. F-Tile CPRI PHY Altera FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Altera FPGA IP Design Example User Guide

Back to home page