Viterbi IP Core User Guide - 2017-11-06

Version: 17.1
Source Name: DITA

1. About the Viterbi IP Core
1.1. Altera DSP IP Core Features
1.2. Viterbi IP Core Features
1.3. DSP IP Core Device Family Support
1.4. DSP IP Core Verification
1.5. Viterbi IP Core Release Information
1.6. Viterbi IP Core Performance and Resource Utilization
2. Viterbi IP Core Getting Started
2.1. Installing and Licensing Intel FPGA IP Cores
2.1.1. Intel FPGA IP Evaluation Mode
2.1.2. Viterbi IP Core Intel FPGA IP Evaluation Mode Timeout Behavior
2.2. IP Catalog and Parameter Editor
2.3. Generating IP Cores ( Intel Quartus Prime Pro Edition)
2.3.1. IP Core Generation Output ( Intel Quartus Prime Pro Edition)
2.4. Simulating Intel FPGA IP Cores
2.5. DSP Builder for Altera FPGAs Design Flow
3. Viterbi IP Core Functional Description
3.1. Decoder
3.2. Convolutional Encoder
3.3. Trellis Coded Modulation
3.3.1. Half-Rate Convolutional Codes
3.3.2. Trellis Decoder
3.3.3. About Converting Received Signals
3.3.4. Trellis Termination
3.3.5. Trellis Initialization
3.4. Viterbi IP Core Parameters
3.4.1. Architecture
3.4.1.1. BER Estimator
3.4.1.2. Node Synchronization
3.4.2. Code Sets
3.4.3. Viterbi Parameters
3.4.3.1. Soft Symbol Input
3.4.3.2. State Metrics
3.4.3.3. Throughput Calculator
3.4.3.4. Latency Calculator
3.4.4. Test Data
3.4.4.1. External Puncturing
3.5. Viterbi IP Core Interfaces and Signals
3.5.1. Avalon-ST Interfaces in DSP IP Cores
3.5.2. Global Signals
3.5.3. Avalon-ST Sink Signals
3.5.4. Avalon Source-ST Signals
3.5.5. Configuration Signals
3.5.6. Status Signals
3.5.7. Viterbi IP Core Timing Diagrams
A. Viterbi IP Core User Guide Document Archives
4. Document Revision History

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