P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide - This IP is a companion tile for Intel Agilex® and Intel Stratix 10 DX devices. It supports an Avalon® memory-mapped interface with up to a Gen4 x16, 512-bit data width to the Application Layer. - 2021-12-25

Version

20-3-3-1-0