AN 875: Intel Stratix 10 E-Tile PCB Design Guidelines - Intel Stratix 10 E-Tile PCB guidelines. The document provides additional information to existing application notes on PCB design. - 2019-03-12

1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
2.1. Intel Stratix 10 E-Tile Transceiver Channel Usage Mode
2.2. Intel Stratix 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2)
2.3. PCB Design Flow
2.3.1. Design Target at 56 Gbps PAM4 Standard
2.3.2. PCB Materials and Stackup Design
2.3.2.1. Insertion Loss
2.3.2.2. Return Loss
2.3.2.3. Package Loss and Crosstalk
2.3.2.4. PCB Via Design
2.3.2.5. PCB Connector
2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design
2.3.3.1. FPGA PCB Breakout Design and Reference
2.3.3.2. P/N De-skew Strategy on Differential Pairs
2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
2.3.4. PCB Pre-Layout Simulation Phase
2.3.5. PCB Post-Layout Simulation Phase
3. Document Revision History for AN 875: Intel Stratix 10 E-Tile PCB Design Guidelines

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