1.1. Open the Example Design - The PLL_RAM example design includes Altera FPGA IP cores to demonstrate the basic simulation flow. Download the example design files and open the project in the Quartus Prime software. - 2025-12-15

ModelSim – FPGA Edition Simulation Quick-Start Quartus Prime Standard Edition
Version
18.0
The PLL_RAM example design includes Altera® FPGA IP cores to demonstrate the basic simulation flow. Download the example design files and open the project in the Quartus® Prime software.
Note: This Quick-Start requires a basic understanding of hardware description language syntax and the Quartus® Prime design flow, as the Quartus® Prime Standard Edition Foundation Online Training describes.
  1. Download and unzip the Quartus_STD_LITE_PLL_RAM.zip design example.
  2. Launch the Quartus® Prime Standard Edition software.
  3. To open the example design project, click File > Open Project, select the pll_ram.qpf project file, and then click OK.