1.5. Add Signals to the Simulation - The CLOCK , WE , OFFSET , RESET_N , and RD_DATA signals automatically appear in the Wave window because the top-level design defines these I/O. In addition, you can optionally add internal signals to the simulation. - 2025-12-15

ModelSim – FPGA Edition Simulation Quick-Start Quartus Prime Standard Edition

Version
18.0
The CLOCK, WE, OFFSET, RESET_N, and RD_DATA signals automatically appear in the Wave window because the top-level design defines these I/O. In addition, you can optionally add internal signals to the simulation.
  1. In the Objects window, locate the UP_module, DOWN_module, PLL_module, and RAM_module modules.
  2. In the Objects window, select RAM_module. The module's inputs and outputs display.
    Figure 8. Add Signals To Wave Window
  3. To add the internal signals between the down-counter and dual-port RAM module, right-click rdaddress and then click Add Wave.
  4. To add the internal signals between the up-counter and dual-port RAM module, right-click wraddress and then click Add Wave. Alternatively, you can drag and drop these signals from the Objects window to the Wave window.
  5. To generate the waveforms for the new signals you add, click Simulate > Run > Continue.