4.3.3. Specifications - 2025-12-15

Agilex™ 7 Embedded Memory User Guide

Version: 25.1

1. Agilex™ 7 Embedded Memory Overview
1.1. Agilex™ 7 Embedded Memory Features
2. Agilex™ 7 Embedded Memory Architecture and Features
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks
2.2.1. Byte Enable Controls
2.2.2. Data Byte Output
2.2.3. Byte Enable Behavior
2.3. Address Clock Enable Support
2.4. Asynchronous Clear and Synchronous Clear
2.5. Memory Blocks Error Correction Code (ECC) Support
2.5.1. Error Correction Code Truth Table
2.5.2. Parity Bit
2.5.3. ECC Parity Flip
2.5.4. ECC Read-During-Write Behavior
2.6. Agilex™ 7 Embedded Memory Clocking Modes
2.6.1. Single Clock Mode
2.6.2. Read/Write Clock Mode
2.6.3. Input/Output Clock Mode
2.6.4. Asynchronous/Synchronous Clears in Clocking Modes
2.6.5. Output Read Data in Simultaneous Read/Write
2.6.6. Independent Clock Enables in Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations
2.7.1. Mixed-Width Port Configurations
2.8. Force-to-Zero
2.9. Coherent Read Memory
2.9.1. Forwarding Logic
2.10. Freeze Logic
2.11. True Dual Port Dual Clock Emulator
2.11.1. True Dual-Port Mixed Port Read During Write New Data Emulation
2.12. Initial Value of Read and Write Address Registers
2.13. Timing/Power Optimization Feature in M20K Blocks
2.14. Agilex™ 7 Supported Embedded Memory IPs
3. Agilex™ 7 Embedded Memory Design Considerations
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Read-During-Write (RDW)
3.3.1. Customize Read-During-Write Behavior
3.3.1.1. Same-Port Read-During-Write Mode
3.3.1.2. Mixed-Port Read-During-Write Mode
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Advanced Settings in Quartus Prime Software for Memory
3.9. Consider the Memory Depth Setting
3.10. M20K Embedded Memory Block Input Clock Quality Requirement
3.11. Consider Registering the Memory Output
4. Agilex™ 7 Embedded Memory IP References
4.1. On-Chip Memory RAM and ROM IPs
4.1.1. Release Information for RAM and ROM IPs
4.1.2. RAM: 1-PORT FPGA IP Parameters
4.1.3. RAM: 2-PORT FPGA IP Parameters
4.1.4. RAM: 4-PORT FPGA IP Parameters
4.1.5. ROM: 1-PORT FPGA IP Parameters
4.1.6. ROM: 2-PORT FPGA IP Parameters
4.1.7. Changing Parameter Settings Manually
4.1.7.1. RAM and ROM Parameter Settings
4.1.8. RAM and ROM Interface Signals
4.2. eSRAM Agilex™ FPGA IP
4.2.1. Release Information for eSRAM Agilex™ FPGA IP
4.2.2. eSRAM System Features
4.2.2.1. eSRAM Specifications
4.2.3. eSRAM Agilex™ FPGA IP Parameters
4.2.4. eSRAM Agilex™ FPGA IP Interface Signals
4.2.5. eSRAM Timing Diagrams
4.3. FIFO IP
4.3.1. Release Information for FIFO IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.3.1. Verilog HDL Prototype
4.3.3.2. VHDL Component Declaration
4.3.3.3. VHDL LIBRARY-USE Declaration
4.3.3.4. HDL Code from Parameterizable Macros Template
4.3.3.5. FIFO Signals
4.3.3.6. FIFO Parameter Settings
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.11.1. Embedded Timing Constraint
4.3.11.2. User Configurable Timing Constraint
4.3.11.2.1. SDC Commands
4.3.12. Coding Example for Manual Instantiation
4.3.13. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.14. Guidelines for Embedded Memory ECC Feature
4.3.15. FIFO IP Parameters
4.3.16. Reset Scheme
4.4. Shift Register (RAM-based) FPGA IP
4.4.1. Release Information for Shift Register (RAM-based) FPGA IP
4.4.2. Shift Register (RAM-based) FPGA IP
4.4.3. Shift Register (RAM-based) FPGA IP General Description
4.4.4. Shift Register (RAM-based) FPGA IP Parameter Settings
4.4.5. Shift Register Ports and Parameters Setting
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide

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