| Parameter | Type | Required | Description |
|---|---|---|---|
| lpm_width | Integer | Yes |
Specifies the width of the data and q ports for the SCFIFO function and DCFIFO function. For the DCFIFO_MIXED_WIDTHS function, this parameter specifies only the width of the data port. |
| lpm_width_r 24 | Integer | Yes |
Specifies the width of the q port for the DCFIFO_MIXED_WIDTHS function. |
| lpm_widthu | Integer | Yes | Specifies the width of the usedw port for the SCFIFO function, or the width of the rdusedw and wrusedw ports for the DCFIFO function. For the DCFIFO_MIXED_WIDTHS function, it only represents the width of the wrusedw port. |
| lpm_widthu_r 24 | Integer | Yes | Specifies the width of the rdusedw port for the DCFIFO_MIXED_WIDTHS function. |
| lpm_numwords | Integer | Yes | Specifies the depths of the FIFO
you require. The value must be at least 4. The value assigned must comply to the following equation: 2^LPM_WIDTHU |
| lpm_showahead | String | Yes | Specifies whether the FIFO is in
normal mode (OFF) or show-ahead mode (ON). For more details, refer
to SCFIFO and DCFIFO Look-Ahead Mode
section. If you set the parameter to ON, you may reduce performance. |
| lpm_type | String | No | Identifies the library of parameterized modules (LPM) entity name. The values are SCFIFO and DCFIFO. |
| lpm_hint | String | No |
This is a legacy parameter that is used to set the following:
Options should be concatenated with a comma in between and enclosed with double quotations. The order does not matter. For example: lpm_hint = ”MAXIMUM_DEPTH=512, RAM_BLOCK_TYPE=M20K, DISABLE_REG_POWER_UP_VALUE=TRUE, DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE” |
| overflow_checking | String | No | Specifies whether or not to enable the protection circuitry for overflow checking that disables the wrreq port when the FIFO IP is full. The values are ON or OFF. If omitted, the default is ON. |
| underflow_checking | String | No | Specifies whether or not to
enable the protection circuitry for underflow checking that disables
the rdreq port when the FIFO IP is empty. The values are
ON or OFF. If omitted, the
default is ON. Note that reading from an empty SCFIFO gives unpredictable results. |
| enable_ecc 25 | String | No | Specifies whether to enable the
error checking and correcting (ECC) feature that corrects single bit
errors, double adjacent bit errors, and detects triple adjacent bit
errors at the output of the memory. This option is only available using M20K memory block
type. The ECC is disabled by default. |
| delay_wrusedw 26 | String | No | Specify the number of register
stages that you want to internally add to the rdusedw or
wrusedw port using the respective parameter. The default value of 1 adds a single register stage to the output to improve its performance. Increasing the value of the parameter does not increase the maximum system speed. It only adds additional latency to the respective output port. |
| add_usedw_msb_bit | String | No | Increases the width of the rdusedw and wrusedw ports by one bit. By increasing the width, it prevents the FIFO IP from rolling over to zero when it is full. The values are ON or OFF. If omitted, the default value is OFF. |
| rdsync_delaypipe | Integer | No | Specify the number of
synchronization stages in the cross clock domain. The value of the
rdsync_delaypipe parameter relates the synchronization
stages from the write control logic to the read control logic; the
wrsync_delaypipe parameter relates the synchronization
stages from the read control logic to the write control logic. Use these parameters to set the number of
synchronization stages if the clocks are not synchronized, and
set the clocks_are_synchronized parameter to FALSE.
The actual synchronization stage implemented relates variously to the parameter value assigned, depends on the target device. The values of these parameters are internally reduced by two. Thus, the default value of 3 for these parameters corresponds to a single synchronization stage; a value of 4 results in two synchronization stages, and so on. Choose at least 4 (two synchronization stages) for metastability protection. |
| use_eab | String | No | Specifies whether or not the FIFO
IP is constructed using the RAM blocks. The values are ON or
OFF. Setting this parameter value to OFF yields the FIFO IP implemented in ALMs regardless of the type of the TriMatrix memory block type assigned to the ram_block_type parameter. This parameter is enabled by default. FIFO is implemented using RAM blocks specified in ram_block_type. |
| write_aclr_synch | String | No | Specifies whether or not to add
a circuit that causes the aclr port to be internally
synchronized by the wrclk clock. Adding the
circuit prevents the race condition between the wrreq and
aclr ports that could corrupt the FIFO IP. The values are ON or OFF. If omitted, the default value is OFF. |
| read_aclr_synch | String | No | Specifies whether or not to add
a circuit that causes the aclr port to be internally
synchronized by the rdclk clock. Adding the
circuit prevents the race condition between the rdreq and
aclr ports that could corrupt the FIFO IP. The values are ON or OFF. If omitted, the default value is OFF. |
| clocks_are_synchronized 26 | String | No | Specifies whether or not the
write and read clocks are synchronized which in turn determines the
number of internal synchronization stages added for stable operation
of the FIFO. The values are TRUE and FALSE.
If omitted, the default value is FALSE. You must only set
the parameter to TRUE if the write clock
and the read clock are always synchronized and they are multiples of
each other. Otherwise, set this to FALSE to avoid
metastability problems. If the clocks are not synchronized, set the parameter to FALSE, and use the rdsync_delaypipe and wrsync_delaypipe parameters to determine the number of synchronization stages required. |
| ram_block_type | String | No |
Specifies the target device’s TriMatrix Memory Block to be used. To get the proper implementation based on the RAM configuration that you set, allow the Quartus® Prime software to automatically choose the memory type by ignoring this parameter and set the use_eab parameter to ON. This gives the compiler the flexibility to place the memory function in any available memory resource based on the FIFO depth required. Types of RAM block type available; Auto (default), MLAB, M20K and M144K. |
| add_ram_output_register | String | No | Specifies whether to register the q output. The values are ON and OFF. If omitted, the default value is OFF. |
| almost_full_value 27 | Integer | No | Sets the threshold value for the almost_full port. When the number of words stored in the FIFO is greater than or equal to this value, the almost_full port is asserted. |
| almost_empty_value 27 | Integer | No | Sets the threshold value for the almost_empty port. When the number of words stored in the FIFO IP is less than this value, the almost_empty port is asserted. |
| allow_wrcycle_when_full 27 | String | No | Allows you to combine read and write cycles to an already full SCFIFO, so that it remains full. The values are ON and OFF. If omitted, the default is OFF. Use only this parameter when the OVERFLOW_CHECKING parameter is set to ON. |
| intended_device_family | String | No | Specifies the intended device that matches the device set in your Quartus® Prime project. Use only this parameter for functional simulation. |
24 Only applicable
for the DCFIFO_MIXED_WIDTHS function.
25 Not applicable for the
DCFIFO_MIXED_WIDTHS function.
26 Only
applicable for the DCFIFO function.
27 Only applicable for
the SCFIFO function.