The
Quartus® Prime
software fully supports Verilog HDL macros, which you can define with the 'define compiler directive in your
source code.
You can also define macros in the
Quartus® Prime software or on the command line.
To set Verilog HDL macros at the command line for the Quartus® Prime Pro Edition synthesis (quartus_syn) executable, use the following format:
quartus_syn <PROJECT_NAME> --set=VERILOG_MACRO=a=2
This command adds the following new line to the project .qsf file:
set_global_assignment -name VERILOG_MACRO "a=2"
To avoid adding this line to the project .qsf, add this option to the quartus_syn command:
--write_settings_files=off