The
Quartus® Prime Pro Edition
software
supports incremental optimization at each stage of design compilation. In
incremental optimization, you run and optimize each compilation stage independently before
running the next compilation module in sequence. The Compiler preserves the results of each
stage as a snapshot for analysis. When you make changes to your design or constraints, the
Compiler only runs stages impacted by the change.
Following synthesis or any
Fitter stage, you can view results and perform timing
analysis;
modify design RTL or Compiler
settings as
needed; and
then
re-run synthesis or the Fitter and evaluate the results of these changes. Repeat this process
until the module performance meets requirements. This flow maximizes the results at each
stage without
waiting for full compilation results.
Figure 44. Incremental Optimization Flow
| Fitter Stage | Incremental Optimization |
|---|---|
| Plan | After this stage, you can run post-Plan timing analysis to verify timing constraints, and validate cross-clock timing windows. View the placement and properties of the periphery (I/O). |
| Place | After this stage, validate resource and logic utilization in the Compilation Reports, and review placement of design elements in the Chip Planner. |
| Route | After this stage, perform detailed setup and hold timing closure in the Timing Analyzer, and view routing congestion in the Chip Planner. |
| Retime | After this stage, review the Retiming results in the Fitter report and correct any restrictions limiting further retiming optimization. |
Note: The Compiler saves the planned, placed,
routed, and retimed snapshots
during
full compilation only if you turn on Enable Intermediate Fitter
Snapshots (). You can also run any intermediate Fitter stage independently to generate the
snapshot for that stage.