The
Hyperflex®
architecture
includes multiple Hyper-Registers in every routing segment and block input. Maximizing the use
of Hyper-Registers improves the balance of time delays between registers, and mitigates
critical path delays. Fast Forward compilation generates design recommendations to help you to
break performance bottlenecks and maximize use of Hyper-Registers to drive the highest
performance in
Stratix® 10,
Agilex™ 7, and
Agilex™ 5 designs.
Figure 60. Hyper-Registers in
Hyperflex®
Architecture
The Fast Forward compilation reports show precisely where to make the most impact with RTL changes, and the performance benefits you can expect from each change after removing retiming restrictions. The Fast Forward compilation flow includes the following high-level steps:
Figure 61. Fast Forward Compile Flow