1.2. Mapping the Interface Signals - There are several differences in the interface signals between Altera GPIO and Altera PHYLite IP cores. - 2025-12-16

AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
There are several differences in the interface signals between Altera GPIO and Altera PHYLite IP cores.
Table 2.  Mapping the Altera GPIO Interface Signals to Altera PHYLite IP Core
Altera GPIO IP Core Direction Altera PHYLite IP Core
ck Input/Output ref_clk
aclr Input/Output reset
datain Input data_in
dataout_[h/l] Input data_to_core[1:0]
datain_[h/l] Output data_from_core[1:0]
oe Output oe_data
dataout Output data_out
Table 3.  Additional Altera PHYLite Input and Output Signals
PHYLite Direction Description
interface_locked Input/Output Similar to the lock signal from the I/O phase locked loop (IOPLL). Typically the Altera GPIO IP core uses the IOPLL to generate the clock signal.
core_clk_out Input/Output Similar to the clock signal used for periphery-to-core or core-to-periphery transfer in the Altera GPIO IP core.
rdata_en Input Drive this signal high to ensure the input data/strobe port is always ready to receive incoming data.
strobe_in Input Sampling clock for the Altera PHYLite IP core that captures the input data.
strobe_out Output A generated clock/strobe signal from the PHYLite IP core. Similar to the synchronous clock out signal when using the GPIO IP core.
strobe_out_en Output Drive this signal high to ensure the Altera PHYLite IP core is always generating the source synchronous clock/strobe through the strobe_out port.
strobe_out_in[1:0] Output Tie strobe_out_in[0] to high and strobe_out_in[1] to low to generate a clock signal. This interface signal is generated in a similar manner you use the Altera GPIO IP core to generate the clock signal.
rdata_valid Input An output signal from the Altera PHYLite IP core that indicates the IP core has transmitted the data and the data is ready to be captured by the user logic.

Related Information