AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines - 2017-05-08

1. AN 756: Altera GPIO to Altera PHYLite Design Implementation Guidelines
1.1. Implementing the Altera PHYLite Design
1.1.1. Parameter Settings
1.2. Mapping the Interface Signals
1.3. Performance Comparison
1.4. Use Case Examples
1.4.1. Use Case 1: Source Synchronous I/O Interface
1.4.2. Use Case 2: Driving Data from FPGA through GPIO to External Device
1.4.3. Use Case 3: Multiple-Speed Parallel Interfaces
1.4.4. Use Case 4: GPIO Interface Using 3.0V/2.5V I/O Standard
1.4.5. Use Case 5: Generating Output Clock through GPIO Output Pin
1.5. Altera GPIO to Altera PHYLite Design Example
1.5.1. Simulation Diagrams
1.5.2. Design Verification
1.6. Document Revision History

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