Stratix® 10 DX Device Overview - This device overview summarizes Stratix® 10 DX features, and describes the block diagram, family plan, and other Stratix® 10 DX related topics. - 2023-09-07

1. Stratix® 10 DX Device Overview
1.1. Stratix® 10 DX Devices
1.2. Stratix® 10 DX Features Summary
1.3. Stratix® 10 DX Block Diagram
1.4. Stratix® 10 DX Family Plan
1.4.1. Available Options
1.5. Hyperflex® Core Architecture
1.6. Heterogeneous 3D SiP Transceiver Tiles
1.7. Stratix® 10 DX Transceivers
1.7.1. Intel® P-Tile Transceivers and Hard IP
1.7.2. Intel® E-Tile Transceivers and Hard IP
1.8. Heterogeneous 3D Stacked HBM2 DRAM Memory
1.9. External Memory and General Purpose I/O
1.10. Adaptive Logic Module (ALM)
1.11. Core Clocking
1.12. I/O PLLs
1.13. Internal Embedded Memory
1.14. Variable Precision DSP Block
1.15. Hard Processor System (HPS)
1.15.1. Key Features of the Stratix® 10 HPS
1.16. Power Management
1.17. Device Configuration and Secure Device Manager (SDM)
1.18. Device Security
1.19. Configuration via Protocol Using PCI Express®
1.20. Partial and Dynamic Reconfiguration
1.21. Fast Forward Compile
1.22. Single Event Upset (SEU) Error Detection and Correction
1.23. Document Revision History for the Stratix® 10 DX Device Overview

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