Stratix 10 Hard Processor System Technical Reference Manual - Stratix 10 SoC FPGA provides an Arm Cortex -A53 Hard Processor System with a variety of hard IP, dedicated I/O and direct external memory access. - 2026-01-20
Version
25.3.1
Product Type
Device Families > Stratix Families
Device Families > Stratix Families > Stratix 10
Resource Type
Documentation > Reference Manual
Documentation > User Guides
Source Name
DITA
1. Stratix 10 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
2.1. Features of the HPS
2.2. HPS Block Diagram and System Integration
2.2.1. HPS Block Diagram
2.2.2. Cortex-A53 MPCore Processor
2.2.3. Cache Coherency Unit
2.2.4. System Memory Management Unit
2.2.5. HPS Interfaces
2.2.5.1. HPS-FPGA Memory-Mapped Interfaces
2.2.5.2. Other HPS Interfaces
2.2.6. System Interconnect
2.2.6.1. Stratix 10 HPS SDRAM L3 Interconnect
2.2.6.1.1. Stratix 10 HPS SDRAM Scheduler
2.2.6.1.2. Stratix 10 HPS SDRAM Adapter
2.2.7. On-Chip RAM
2.2.7.1. On-Chip RAM
2.2.8. Flash Memory Controllers
2.2.8.1. NAND Flash Controller
2.2.8.2. SD/MMC Controller
2.2.9. System Modules
2.2.9.1. Clock Manager
2.2.9.2. Reset Manager
2.2.9.3. System Manager
2.2.9.4. Timers
2.2.9.5. Watchdog Timers
2.2.9.6. DMA Controller
2.2.9.7. Error Checking and Correction Controller
2.2.10. Interface Peripherals
2.2.10.1. EMACs
2.2.10.2. USB Controllers
2.2.10.3. I2C Controllers
2.2.10.4. UARTs
2.2.10.5. SPI Master Controllers
2.2.10.6. SPI Slave Controllers
2.2.10.7. GPIO Interfaces
2.2.11. CoreSight Debug and Trace
2.2.12. Hard Processor System I/O Pin Multiplexing
2.3. Endian Support
2.4. Stratix 10 Hard Processor System Component Reference Manual
2.5. Introduction to the Hard Processor System Address Map
3. Cortex -A53 MPCore Processor
3.1. Features of the Cortex -A53 MPCore
3.2. Advantages of Cortex -A53 MPCore
3.3. Cortex -A53 MPCore Block Diagram
3.4. Cortex -A53 MPCore System Integration
3.5. Cortex -A53 MPCore Functional Description
3.5.1. Exception Levels
3.5.1.1. Security State
3.5.1.2. Security Model
3.5.2. Virtualization
3.5.2.1. Virtual Interrupts
3.5.3. Memory Management Unit
3.5.3.1. Translation Lookaside Buffers
3.5.3.2. Translation Match Process
3.5.4. Level 1 Caches
3.5.4.1. Instruction Cache
3.5.4.2. Data Cache
3.5.4.2.1. ACE Transactions
3.5.4.2.2. Data Prefetching
3.5.4.3. Initializing the Instruction and Data Caches
3.5.5. Level 2 Memory System
3.5.6. Snoop Control Unit
3.5.6.1. Implementation Details
3.5.7. Cryptographic Extensions
3.5.8. NEON Multimedia Processing Engine
3.5.8.1. Single Instruction, Multiple Data (SIMD) Processing
3.5.8.2. Features of the NEON MPE
3.5.9. Floating Point Unit
3.5.10. ACE Bus Interface
3.5.11. Abort Handling
3.5.12. Cache Protection
3.5.12.1. Error Reporting
3.5.13. Generic Interrupt Controller
3.5.13.1. GIC Block Diagram
3.5.13.2. GIC Clock
3.5.13.3. GIC Reset
3.5.13.4. GIC Interrupt Map for the SoC HPS
3.5.14. Generic Timers
3.5.14.1. System Counter
3.5.15. Debug Modules
3.5.15.1. ARMv8 Debug
3.5.15.2. Interactive Debugging Features
3.5.15.3. Performance Monitor Unit
3.5.15.4. Embedded Trace Macrocell
3.5.15.4.1. Embedded Trace Macrocell Reset
3.5.15.5. Program Trace
3.5.15.6. Event Trace
3.5.15.7. Cross Trigger Interface
3.5.16. Cache Coherency Unit
3.5.17. Clock Sources
3.6. Cortex -A53 MPCore Programming Guide
3.6.1. Enabling Cortex -A53 MPCore Clocks
3.6.2. Bringing the Cortex -A53 MPCore out of Reset
3.6.3. Enabling and Disabling Cache
3.6.4. Entering Low Power Modes
3.7. Cortex -A53 MPCore Address Map
4. Cache Coherency Unit
4.1. Supported Features
4.2. Block Diagram
4.3. CCU Connectivity
4.4. CCU System Integration
4.5. Functional Description
4.5.1. Bridges
4.5.1.1. Bridge Registers
4.5.2. Cache Coherency Controller
4.5.2.1. Coherency Directory
4.5.2.1.1. ECC Protection
4.5.2.2. Speculative Fetch
4.5.3. I/O Coherency Bridge
4.5.4. Distributed Virtual Memory Controller
4.5.5. Cache Coherency Unit Traffic Management
4.5.5.1. Quality of Service
4.5.5.2. Transmit Rate Limiters
4.5.5.2.1. Rate Limiter Configuration
4.5.6. Cache Coherency Unit Interrupts
4.5.7. Cache Coherency Unit Clocks
4.5.8. Cache Coherency Unit Reset
4.6. Cache Coherency Unit Transactions
4.6.1. Command Mapping
4.7. Programming Guidelines
4.7.1. Enabling Interrupts
4.7.2. Disabling the FPGA-to-HPS Interface to CCU
4.7.3. Specifying Address Ranges for Slave Devices
4.7.4. Accessing and Testing the Coherency Directory RAM
4.7.5. Secure and Non-secure Transactions
4.8. Cache Coherency Unit Address Map and Register Definitions
5. System Memory Management Unit
5.1. System Memory Management Unit Features
5.2. System MMU Block Diagram
5.2.1. System Memory Management Unit Interfaces
5.3. System Integration
5.4. System Memory Management Unit Functional Description
5.4.1. Translation Stages
3.5.1. Exception Levels
3.5.1.1. Security State
5.4.3. Translation Regimes
5.4.4. Translation Buffer Unit
5.4.4.1. Micro Translation Lookaside Buffer
5.4.5. Translation Control Unit
5.4.5.1. Macro Translation Lookaside Buffer
5.4.6. Security State Determination
5.4.7. Stream ID
5.4.8. Quality of Service Arbitration
5.4.9. System Memory Management Unit Interrupts
5.4.10. System Memory Management Unit Reset
5.4.11. System Memory Management Unit Clocks
5.5. System Memory Management Unit Configuration
5.6. System Memory Management Unit Address Map and Register Definitions
6. System Interconnect
6.1. About the System Interconnect
6.1.1. System Interconnect Block Diagram and System Integration
6.1.1.1. System Interconnect High-Level View
6.1.1.2. Connectivity
6.1.1.2.1. Stratix 10 HPS Master-to-Slave Connectivity Matrix
6.1.1.2.2. Peripherals Connections
6.1.1.2.3. System Connections
6.1.1.2.4. Connections to HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges
6.1.1.2.5. SDRAM Connections
6.1.1.3. System Interconnect Architecture
6.1.1.3.1. SDRAM L3 Interconnect Architecture
6.1.2. Stratix 10 HPS Secure Firewalls
6.1.3. About the Rate Adapter
6.1.4. About the SDRAM L3 Interconnect
6.1.4.1. Features of the Stratix 10 HPS SDRAM L3 Interconnect
6.1.4.2. SDRAM L3 Interconnect Block Diagram and System Integration
6.1.4.3. About the SDRAM Scheduler
6.1.5. About Arbitration and Quality of Service
6.1.6. About the Service Network
6.1.7. About the Observation Network
6.2. Functional Description of the Stratix 10 HPS System Interconnect
6.2.1. Stratix 10 System Interconnect Address Spaces
6.2.1.1. HPS-to-FPGA Bridge Address Spaces
6.2.1.2. Stratix 10 HPS L3 Address Space
6.2.1.3. Stratix 10 MPU Address Space
6.2.1.4. HPS SDRAM Address Space
6.2.1.5. Example (Recommended) System Memory Mapping Scheme
6.2.2. Secure Transaction Protection
6.2.3. Stratix 10 HPS System Interconnect Master Properties
6.2.3.1. Stratix 10 HPS Master Caching and Buffering Overrides
6.2.3.2. Stratix 10 HPS Cacheable Transfer Routing
6.2.4. Stratix 10 HPS System Interconnect Slave Properties
6.2.5. System Interconnect Clocks
6.2.5.1. Clock Domains
6.2.5.1.1. Main Clock Domain
6.2.5.1.2. Lightweight HPS-to-FPGA Clock Domain
6.2.5.1.3. HPS-to-FPGA Clock Domain
6.2.6. Stratix 10 HPS System Interconnect Resets
6.2.7. Functional Description of the Rate Adapters
6.2.8. Functional Description of the Firewalls
6.2.8.1. Security
6.2.8.1.1. System Interconnect Firewalls and Slave Security
6.2.8.1.2. Stratix 10 HPS Slave Security
6.2.8.1.3. Stratix 10 HPS Master Security
6.2.9. Functional Description of the SDRAM L3 Interconnect
6.2.9.1. Functional Description of the Stratix 10 HPS SDRAM Scheduler
6.2.9.1.1. Monitors for Mutual Exclusion
6.2.9.1.2. Arbitration and Quality of Service in the SDRAM Scheduler
6.2.9.2. Functional Description of the SDRAM Adapter
6.2.9.2.1. ECC
6.2.9.2.1.1. ECC Write Behavior
6.2.9.2.1.2. ECC Read Behavior
6.2.9.2.2. SDRAM Adapter Interrupt Support
6.2.9.2.3. SDRAM Adapter Clocks
6.2.9.3. SDRAM L3 Firewalls
6.2.9.4. SDRAM L3 Interconnect Resets
6.2.10. Functional Description of the Arbitration Logic
6.2.11. Functional Description of the Observation Network
6.2.11.1. Stratix 10 HPS Interconnect Probes
6.2.11.2. Stratix 10 Packet Tracing, Profiling, and Statistics
6.2.11.2.1. Packet Filtering
6.2.11.2.2. Statistics Collection
6.2.11.2.3. Stratix 10 EMAC Transaction Profiling
6.2.11.3. Packet Alarms
6.2.11.4. Error Logging
6.3. Configuring the System Interconnect
6.3.1. Configuring the Rate Adapter
6.3.2. Configuring the SDRAM Scheduler
6.3.2.1. Stratix 10 HPS FPGA Port Configuration
6.3.2.2. Memory Timing Configuration
6.3.3. Configuring the Hard Memory Controller
6.3.3.1. SDRAM Adapter Memory Mapped Registers
6.3.3.2. Hard Memory Controller Memory Mapped Registers
6.4. Peripheral Region Address Map
6.5. System Interconnect Registers
6.6. System Interconnect Address Map and Register Definitions
7. HPS-FPGA Bridges
7.1. Features of the HPS-FPGA Bridges
7.2. HPS-FPGA Bridges Block Diagram and System Integration
7.3. FPGA-to-HPS Bridge
7.3.1. FPGA-to-HPS and FPGA-to-SDRAM Restrictions
7.3.1.1. FPGA-to-SDRAM direct ( AXI 4)
7.3.1.2. FPGA-to-HPS CCU (ACE-lite)
7.3.1.3. AxPROT[2:0] Considerations
7.3.2. FPGA-to-SDRAM Example Transactions
7.3.2.1. FPGA-to-SDRAM direct (Cache Non-Allocate)
7.3.3. FPGA-to-HPS Example Transactions
7.3.3.1. FPGA-to-HPS CCU to SDRAM/OCRAM Memory (Cache Non-Allocate)
7.3.3.2. FPGA-to-HPS CCU to SDRAM/OCRAM Memory (Cache Allocate)
7.3.3.3. FPGA-to-HPS CCU to Peripherals (Device Non-Bufferable)
7.4. HPS-to-FPGA Bridge
7.4.1. HPS-to-FPGA Bridge Signals
7.5. Lightweight HPS-to-FPGA Bridge
7.6. Clocks and Resets
7.6.1. FPGA-to-HPS Bridge Clocks and Resets
7.6.2. HPS-to-FPGA Bridge Clocks and Resets
7.6.3. Lightweight HPS-to-FPGA Bridge Clocks and Resets
7.6.4. Taking HPS-FPGA Bridges Out of Reset
7.7. Data Width Sizing
7.8. Ready Latency Support
7.9. HPS-FPGA Bridges Address Map and Register Definitions
8. DMA Controller
8.1. Features of the DMA Controller
8.2. DMA Controller Block Diagram and System Integration
8.2.1. Distributed Virtual Memory Support
8.3. Functional Description of the DMA Controller
8.3.1. Error Checking and Correction
8.3.1.1. Initializing and Clearing of Memory before Enabling ECC
8.3.2. Peripheral Request Interface
8.3.2.1. Handshake Rules
8.3.2.2. Peripheral Request Interface Mapping
8.4. DMA Controller Address Map and Register Definitions
9. On-Chip RAM
9.1. Features of the On-Chip RAM
9.2. On-Chip RAM Block Diagram and System Integration
9.3. Functional Description of the On-Chip RAM
9.3.1. Read and Write Double-Bit Bus Errors
9.3.2. On-Chip RAM Controller
9.3.3. On-Chip RAM Burst Support
9.3.4. Exclusive Access Support
9.3.5. Sub-word Accesses
9.3.5.1. Pipeline and Timing
9.3.6. On-Chip RAM Clocks
9.3.7. On-Chip RAM Resets
9.3.8. On-Chip RAM Initialization
9.3.9. ECC Protection
9.4. On-Chip RAM Address Map and Register Definitions
10. Error Checking and Correction Controller
10.1. ECC Controller Features
10.2. ECC Supported Memories
10.3. ECC Controller Block Diagram and System Integration
10.4. ECC Controller Functional Description
10.4.1. Overview
10.4.2. ECC Structure
10.4.2.1. RAM and ECC Memory Organization Example
10.4.3. Memory Data Initialization
10.4.4. Indirect Memory Access
10.4.4.1. Watchdog Timer
10.4.4.2. Data Correction
10.4.4.3. Error Injection
10.4.4.4. Memory Testing
10.4.4.4.1. Register Interface Tests
10.4.4.4.1.1. Single-Bit Error Test for DMA ECC RAM
10.4.4.4.1.2. Single-Bit Error Test for Word-Writeable Memories
10.4.4.4.1.3. Double-Bit Error Test
10.4.4.4.2. Peripheral Slave Interface Tests for DMA ECC RAM
10.4.4.5. Error Checking and Correction Algorithm
10.4.5. Error Logging
10.4.5.1. Recent Error Address Registers
10.4.5.2. Single-Bit Error Occurrence
10.4.5.3. Single-Bit Error Look-Up Table
10.4.6. ECC Controller Interrupts
10.4.6.1. Single-Bit Error Interrupts
10.4.6.1.1. All Single-Bit Error Interrupt
10.4.6.1.2. LUT Overflow Interrupt
10.4.6.1.3. Counter Match Interrupt
10.4.6.2. Double-Bit Error Interrupt
10.4.6.3. Interrupt Testing
10.4.7. ECC Controller Initialization and Configuration
10.4.8. ECC Controller Clocks
10.4.9. ECC Controller Reset
10.5. ECC Controller Address Map and Register Descriptions
11. Clock Manager
11.1. Features of the Clock Manager
11.2. Top Level Clocks
11.2.1. Boot Clock
11.3. Functional Description of the Clock Manager
11.3.1. Clock Manager Building Blocks
11.3.1.1. PLLs
11.3.1.2. Clock Gating
11.3.2. PLL Integration
11.3.3. Hardware-Managed and Software-Managed Clocks
11.3.4. Hardware Sequenced Clock Groups
11.3.5. Software Sequenced Clocks
11.3.6. Resets
11.3.7. Security
11.3.8. Interrupts
11.4. Clock Manager Address Map and Register Definitions
12. Reset Manager
12.1. Functional Description
12.1.1. HPS_COLD_nRESET Pin Function
12.2. Modules Under Reset
12.3. Reset Handshaking
12.4. Reset Sequencing
12.4.1. HPS-to-FPGA Reset Sequence
12.4.2. Warm Reset Sequence
12.4.3. Watchdog Reset Sequence
12.5. Reset Signals and Registers
12.6. Reset Manager Address Map and Register Definitions
13. System Manager
13.1. Features of the System Manager
13.2. System Manager Block Diagram
13.3. Functional Description of the System Manager
13.3.1. Additional Module Control
13.3.1.1. DMA Controller
13.3.1.2. NAND Flash Controller
13.3.1.3. EMAC
13.3.1.4. USB 2.0 OTG Controller
13.3.1.5. SD/MMC Controller
13.3.1.6. GPIO Interconnect Between the HPS and FPGA
13.3.1.7. Watchdog Timer
13.3.2. FPGA Interface Enables
13.3.3. ECC and Parity Control
13.3.4. Preloader Handoff Information
13.3.5. Clocks
13.3.6. Resets
13.4. System Manager Address Map and Register Definitions
14. Hard Processor System I/O Pin Multiplexing
14.1. Features of the Stratix 10 HPS I/O Block
14.2. Stratix 10 HPS I/O System Integration
14.3. Functional Description of the HPS I/O
14.3.1. I/O Pins
14.3.2. FPGA Access
14.3.3. Stratix 10 I/O Control Registers
14.3.3.1. Stratix 10 Dedicated Pin MUX Registers
14.3.3.2. Stratix 10 Dedicated Configuration Registers
14.3.3.3. FPGA Access MUX Registers
14.3.3.4. HPS Oscillator Clock Input Register
14.3.3.5. HPS JTAG Pin MUX Register
14.3.4. Configuring HPS I/O Multiplexing
14.3.4.1. Configuring Stratix 10 I/O Multiplexing at System Generation
14.4. Stratix 10 Pin MUX Test Considerations
14.5. Stratix 10 I/O Pin MUX Address Map and Register Definitions
15. NAND Flash Controller
15.1. NAND Flash Controller Features
15.2. NAND Flash Controller Block Diagram and System Integration
15.2.1. Distributed Virtual Memory Support
15.3. NAND Flash Controller Signal Descriptions
15.4. Functional Description of the NAND Flash Controller
15.4.1. Discovery and Initialization
15.4.2. Bootstrap Interface
15.4.2.1. Bootstrap Setting Bits
15.4.3. Configuration by Host
15.4.3.1. Recommended Bootstrap Settings for 512-Byte Page Device
15.4.4. Local Memory Buffer
15.4.5. Clocks
15.4.5.1. Clock Generation
15.4.5.2. Clock Enable
15.4.5.3. Clock Switching
15.4.6. Resets
15.4.6.1. Taking the NAND Flash Controller Out of Reset
15.4.7. Indexed Addressing
15.4.7.1. Register Map for Indexed Addressing
15.4.7.2. Indexed Addressing Host Usage
15.4.8. Command Mapping
15.4.8.1. MAP00 Commands
15.4.8.1.1. MAP00 Command Format
15.4.8.1.2. MAP00 Usage Limitations
15.4.8.2. MAP01 Commands
15.4.8.2.1. MAP01 Command Format
15.4.8.2.2. MAP01 Usage Limitations
15.4.8.3. MAP10 Commands
15.4.8.3.1. MAP10 Command Format
15.4.8.3.2. MAP10 Operations
15.4.8.3.3. MAP10 Usage Limitations
15.4.8.4. MAP11 Commands
15.4.8.4.1. MAP11 Control Format
15.4.8.4.2. MAP11 Usage Limitations
15.4.9. Data DMA
15.4.9.1. Multi-Transaction DMA Command
15.4.9.1.1. Command-Data Pair Formats
15.4.9.1.2. Using Multi-Transaction DMA Commands
15.4.9.2. Burst DMA Command
15.4.10. ECC
15.4.10.1. Correction Capability, Sector Size, and Check Bit Size
15.4.10.2. ECC Programming Modes
15.4.10.3. Main Area Transfer Mode
15.4.10.4. Spare Area Transfer Mode
15.4.10.5. Main+Spare Area Transfer Mode
15.4.10.6. Preserving Bad Block Markers
15.4.10.7. Error Correction Status
15.5. NAND Flash Controller Programming Model
15.5.1. Basic Flash Programming
15.5.1.1. NAND Flash Controller Optimization Sequence
15.5.1.2. Device Initialization Sequence
15.5.1.3. Device Operation Control
15.5.1.4. ECC Enabling
15.5.1.5. NAND Flash Controller Performance Registers
15.5.1.6. Interrupt and DMA Enabling
15.5.1.6.1. Order of Interrupt Status Bits Assertion
15.5.1.7. Timing Registers
15.5.1.8. Registers to Ignore
15.5.2. Flash-Related Special Function Operations
15.5.2.1. Erase Operations
15.5.2.1.1. Single Block Erase
15.5.2.1.2. Multi-Plane Erase
15.5.2.2. Lock Operations
15.5.2.2.1. Unlocking a Span of Memory Blocks
15.5.2.2.2. Locking All Memory Blocks
15.5.2.2.3. Setting Lock-Tight on All Memory Blocks
15.5.2.3. Transfer Mode Operations
15.5.2.3.1. transfer_spare_reg and MAP10 Transfer Mode Commands
15.5.2.3.2. Configure for Default Area Access
15.5.2.3.3. Configure for Spare Area Access
15.5.2.3.4. Configure for Main+Spare Area Access
15.5.2.4. Read-Modify-Write Operations
15.5.2.4.1. Read-Modify-Write Operation Flow
15.5.2.5. Copy-Back Operations
15.5.2.5.1. Copying a Memory Area (Single Plane)
15.5.2.5.2. Copying a Memory Area (Multi-Plane)
15.5.2.6. Pipeline Read-Ahead and Write-Ahead Operations
15.5.2.6.1. Pipeline Read-Ahead Function
15.5.2.6.2. Set Up a Single Area for Pipeline Read-Ahead
15.5.2.6.3. Pipeline Write-Ahead Function
15.5.2.6.4. Set Up a Single Area for Pipeline Write-Ahead
15.5.2.6.5. Other Supported Commands
15.6. NAND Flash Controller Address Map and Register Definitions
16. SD/MMC Controller
16.1. Features of the SD/MMC Controller
16.1.1. SD Card Support Matrix
16.1.2. MMC Support Matrix
16.2. SD/MMC Controller Block Diagram and System Integration
16.2.1. Distributed Virtual Memory Support
16.3. SD/MMC Controller Signal Description
16.4. Functional Description of the SD/MMC Controller
16.4.1. SD/MMC/CE-ATA Protocol
16.4.2. BIU
16.4.2.1. Slave Interface
16.4.2.2. Register Block
16.4.2.2.1. Registers Locked Out Pending Command Acceptance
16.4.2.3. FIFO Buffer
16.4.2.4. Interrupt Controller Unit
16.4.2.4.1. Interrupt Setting and Clearing
16.4.2.5. Internal DMA Controller
16.4.2.5.1. Internal DMA Controller Descriptors
16.4.2.5.2. Internal DMA Controller Descriptor Address
16.4.2.5.3. Internal DMA Controller Descriptor Fields
16.4.2.5.4. Host Bus Burst Access
16.4.2.5.5. Host Data Buffer Alignment
16.4.2.5.6. Buffer Size Calculations
16.4.2.5.7. Internal DMA Controller Interrupts
16.4.2.5.8. Internal DMA Controller Functional State Machineâ€
16.4.2.6. Abort During Internal DMA Transfer
16.4.2.7. Fatal Bus Error Scenarios
16.4.2.7.1. FIFO Buffer Overflow and Underflow
16.4.2.7.2. PBL and Watermark Levels
16.4.3. CIU
16.4.3.1. Command Path
16.4.3.1.1. Load Command Parameters
16.4.3.1.2. Send Command and Receive Response
16.4.3.1.3. Send Response to BIU
16.4.3.1.4. Driving P-bit to the CMD Pin
16.4.3.1.5. Polling the CCS
16.4.3.1.6. CCS Detection and Interrupt to Host Processor
16.4.3.1.7. CCS Timeout
16.4.3.1.8. Send CCSD Command
16.4.3.1.9. I/O transmission delay (NACIO Timeout)
16.4.3.2. Data Path
16.4.3.2.1. Data Transmit
16.4.3.2.1.1. Stream Data Transmit
16.4.3.2.1.2. Single Block Data
16.4.3.2.1.3. Multiple Block Data
16.4.3.2.2. Data Receive
16.4.3.2.2.1. Stream Data Read
16.4.3.2.2.2. Single-block Data Read
16.4.3.2.2.3. Multiple-block Data Read
16.4.3.2.3. Auto-Stop
16.4.3.2.3.1. Auto-Stop Generation for MMC Cards
16.4.3.2.3.2. Auto-Stop Generation for SD Cards
16.4.3.2.3.3. Auto-Stop Generation for SDIO Cards
16.4.3.2.4. Non-Data Transfer Commands that Use Data Path
16.4.3.3. Clock Control Block
16.4.3.4. Error Detection
16.4.3.4.1. Responseâ€
16.4.3.4.2. Data Transmitâ€
16.4.3.4.3. Data Receive
16.4.4. Clocks
16.4.5. Resets
16.4.5.1. Taking the SD/MMC Controller Out of Reset
16.4.6. Voltage Switching
16.5. SD/MMC Controller Programming Model
16.5.1. Software and Hardware Restrictionsâ€
16.5.1.1. Avoiding Glitches in the Card Clock Outputsâ€
16.5.1.2. Reading from a Card in Non-DMA Modeâ€
16.5.1.3. Software Issues a Controller_Reset Commandâ€
16.5.1.4. Data-Transfer Requirement Between the FIFO and Hostâ€
16.5.2. Initialization
16.5.2.1. Power-On Reset Sequence
16.5.2.2. Enumerated Card Stack
16.5.2.2.1. Identifying the Connected Card Type
16.5.2.2.1.1. Card Type is Either SDIO COMBO or Still in Initialization
16.5.2.2.1.2. Determine if Card is a CE-ATA 1.1, CE-ATA 1.0, or MMC Device
16.5.2.3. Clock Setup
16.5.2.3.1. Changing the Card Clock Frequency
16.5.2.3.2. Timing Tuning
16.5.3. Controller/DMA/FIFO Buffer Reset Usage
16.5.4. Non-Data Transfer Commands
16.5.4.1. cmd Register Settings for Non-Data Transfer Commandâ€
16.5.5. Data Transfer Commands
16.5.5.1. Confirming Transfer State
16.5.5.2. Busy Signal After CE-ATA RW_BLK Write Transfer
16.5.5.3. Data Transfer Interrupts
16.5.5.4. Single-Block or Multiple-Block Read
16.5.5.4.1. cmd Register Settings for Single-Block and Multiple-Block Readsâ€
16.5.5.5. Single-Block or Multiple-Block Write
16.5.5.5.1. cmd Register Settings for Single-Block and Multiple-Block Write
16.5.5.6. Stream Read and Write
16.5.5.7. Packed Commands
16.5.6. Transfer Stop and Abort Commands
16.5.6.1. STOP_TRANSMISSION (CMD12)
16.5.6.2. ABORT
16.5.6.2.1. Sending the ABORT Command
16.5.6.2.2. cmdarg Register Settings for SD/SDIO ABORT Commandâ€
16.5.7. Internal DMA Controller Operations
16.5.7.1. Internal DMA Controller Initialization
16.5.7.2. Internal DMA Controller Transmission Sequences
16.5.7.3. Internal DMA Controller Reception Sequences
16.5.8. Commands for SDIO Card Devices
16.5.8.1. Suspend and Resume Sequence
16.5.8.1.1. Suspend
16.5.8.1.2. Resume
16.5.8.2. Read-Wait Sequence
16.5.8.2.1. Signaling a Stall
16.5.9. CE-ATA Data Transfer Commands
16.5.9.1. ATA Task File Transfer Overview
16.5.9.2. ATA Task File Transfer Using the RW_MULTIPLE_REGISTER (RW_REG) Command
16.5.9.2.1. Implementing ATA Task File Transfer
16.5.9.2.2. Register Settings for ATA Task File Transfer
16.5.9.2.3. Reset and Card Device Discovery Overview
16.5.9.3. ATA Payload Transfer Using the RW_MULTIPLE_BLOCK (RW_BLK) Command
16.5.9.3.1. Implementing ATA Payload Transfer
16.5.9.3.2. Register Settings for ATA Payload Transfer
16.5.9.4. CE-ATA CCS
16.5.9.4.1. Disabling the CCS
16.5.9.4.2. Recovery after CCS Timeout
16.5.9.4.3. Recovery after I/O Read Transmission Delay (NACIO) Timeout
16.5.9.5. Reduced ATA Command Set
16.5.9.5.1. The IDENTIFY DEVICE Command
16.5.9.5.2. The READ DMA EXT Command
16.5.9.5.3. The WRITE DMA EXT Command
16.5.9.5.4. The STANDBY IMMEDIATE Command
16.5.9.5.5. The FLUSH CACHE EXT Command
16.5.10. Card Read Threshold
16.5.10.1. Recommended Usage Guidelines for Card Read Threshold
16.5.10.2. Card Read Threshold Programming Sequence
16.5.10.3. Card Read Threshold Programming Examples
16.5.11. Interrupt and Error Handling
16.5.12. Booting Operation for eMMC and MMC
16.5.12.1. Boot Operation by Holding Down the CMD Line
16.5.12.2. Boot Operation for eMMC Card Device
16.5.12.3. Boot Operation for Removable MMC4.3, MMC4.4 and MMC4.41 Cards
16.5.12.3.1. Removable MMC4.3, MMC4.4, and MMC4.41 Differences
16.5.12.3.2. Booting Removable MMC4.3, MMC4.4 and MMC4.41 Cards
16.5.12.4. Alternative Boot Operation
16.5.12.5. Alternative Boot Operation for eMMC Card Devices
16.5.12.6. Alternative Boot Operation for MMC4.3 Cards
16.5.12.6.1. Removable MMC4.3 Boot Mode Support
16.5.12.6.2. Discovering Removable MMC4.3 Boot Mode Support
16.6. SD/MMC Controller Address Map and Register Definitions
17. Ethernet Media Access Controller
17.1. Features of the Ethernet MAC
17.1.1. MAC
17.1.2. DMA
17.1.3. Management Interface
17.1.4. Acceleration
17.1.5. PHY Interface
17.2. EMAC Block Diagram and System Integration
17.3. Distributed Virtual Memory Support
17.4. EMAC Controller Signal Description
17.4.1. EMAC Controller I/O Signals
17.4.1.1. HPS-to-PHY Interface Diagrams
17.4.2. FPGA Routing
17.4.3. PHY Management Interface
17.4.3.1. MDIO Interface
17.4.3.2. I2C External PHY Management Interface
17.4.4. PHY Interface Options
17.5. EMAC Internal Interfaces
17.5.1. DMA Master Interface
17.5.2. Timestamp Interface
17.5.3. System Manager Configuration Interface
17.6. Functional Description of the EMAC
17.6.1. Transmit and Receive Data FIFO Buffers
17.6.2. DMA Controller
17.6.2.1. Descriptor Lists and Data Buffersâ€
17.6.2.2. Host Bus Burst Access
17.6.2.3. Host Data Buffer Alignment
17.6.2.3.1. Example: Buffer Read
17.6.2.3.2. Example: Buffer Write
17.6.2.4. Buffer Size Calculations
17.6.2.5. Transmission
17.6.2.5.1. TX DMA Operation: Default (Non-OSF) Mode
17.6.2.5.2. TX DMA Operation: OSF Mode
17.6.2.5.3. Transmit Frame Processing
17.6.2.5.4. Transmit Polling Suspended
17.6.2.6. Reception
17.6.2.6.1. Receive Descriptor Acquisition
17.6.2.6.2. Receive Frame Processing
17.6.2.6.3. Receive Process Suspended
17.6.2.7. Interrupts
17.6.2.8. Error Response to DMA
17.6.3. Descriptor Overview
17.6.3.1. Transmit Descriptor
17.6.3.2. Receive Descriptor
17.6.3.2.1. Receive Descriptor Field 0 (RDES0)
17.6.3.2.2. Receive Descriptor Field 1 (RDES1)
17.6.3.2.3. Receive Descriptor Fields (RDES2) and (RDES3)
17.6.3.2.3.1. Receive Descriptor Field 2 (RDES2)
17.6.3.2.3.2. Receive Descriptor Field 3 (RDES3)
17.6.3.2.4. Receive Descriptor Field 4 (RDES4)
17.6.3.2.5. Receive Descriptor Fields (RDES6) and (RDES7)
17.6.3.2.5.1. Receive Descriptor Field 6 (RDES6)
17.6.3.2.5.2. Receive Descriptor Field 7 (RDES7)
17.6.4. IEEE 1588-2002 Timestamps
17.6.4.1. Reference Timing Source
17.6.4.2. System Time Register Module
17.6.4.3. Transmit Path Functions
17.6.4.4. Receive Path Functions
17.6.4.5. Timestamp Error Margin
17.6.4.6. Frequency Range of Reference Timing Clock
17.6.5. IEEE 1588-2008 Advanced Timestamps
17.6.5.1. Peer-to-Peer PTP Transparent Clock (P2P TC) Message Support
17.6.5.2. Clock Types
17.6.5.2.1. Ordinary Clock
17.6.5.2.2. Boundary Clock
17.6.5.2.3. End-to-End Transparent Clock
17.6.5.2.4. Peer-to-Peer Transparent Clock
17.6.5.3. Reference Timing Source
17.6.5.4. Transmit Path Functions
17.6.5.5. Receive Path Functions
17.6.5.6. Auxiliary Snapshot
17.6.6. IEEE 802.3az Energy Efficient Ethernet
17.6.6.1. LPI Timers
17.6.7. Checksum Offload
17.6.8. Frame Filtering
17.6.8.1. Source Address or Destination Address Filtering
17.6.8.1.1. Unicast Destination Address Filter
17.6.8.1.2. Multicast Destination Address Filter
17.6.8.1.3. Hash or Perfect Address Filter
17.6.8.1.4. Broadcast Address Filter
17.6.8.1.5. Unicast Source Address Filter
17.6.8.1.6. Inverse Filtering Operation (Invert the Filter Match Result at Final Output)
17.6.8.1.7. Destination and Source Address Filtering Summary
17.6.8.2. VLAN Filtering
17.6.8.2.1. VLAN Tag-Based Filtering
17.6.8.2.2. VLAN Hash Filtering with a 16-Bit Hash Table
17.6.8.3. Layer 3 and Layer 4 Filters
17.6.8.3.1. Matched Frames
17.6.8.3.2. Unmatched Frames
17.6.8.3.3. NonTCP or UDP IP Frames
17.6.8.3.4. Layer 3 and Layer 4 Filters Register Set
17.6.8.3.5. Layer 3 Filtering
17.6.8.3.6. Layer 4 Filtering
17.6.9. Clocks and Resets
17.6.9.1. Clock Structure
17.6.9.2. Clock Gating for EEE
17.6.9.3. Reset
17.6.9.3.1. Taking the Ethernet MAC Out of Reset
17.6.10. Interrupts
17.7. Ethernet MAC Programming Model
17.7.1. System Level EMAC Configuration Registers
17.7.2. EMAC FPGA Interface Initialization
17.7.3. EMAC HPS Interface Initialization
17.7.4. DMA Initialization
17.7.5. EMAC Initialization and Configuration
17.7.6. Performing Normal Receive and Transmit Operation
17.7.7. Stopping and Starting Transmission
17.7.8. Programming Guidelines for Energy Efficient Ethernet
17.7.8.1. Entering and Exiting the TX LPI Mode
17.7.8.2. Gating Off the CSR Clock in the LPI Mode
17.7.8.2.1. Gating Off the CSR Clock in the RX LPI Mode
17.7.8.2.2. Gating Off the CSR Clock in the TX LPI Mode
17.7.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
17.7.9.1. Generating a Single Pulse on PPS
17.7.9.2. Generating a Pulse Train on PPS
17.7.9.3. Generating an Interrupt without Affecting the PPS
17.8. Ethernet MAC Address Map and Register Definitions
18. USB 2.0 OTG Controller
18.1. Features of the USB OTG Controller
18.1.1. Supported PHYs
18.2. Block Diagram and System Integration
18.3. Distributed Virtual Memory Support
18.4. USB 2.0 ULPI PHY Signal Description
18.5. Functional Description of the USB OTG Controller
18.5.1. USB OTG Controller Components
18.5.1.1. Master Interface
18.5.1.2. Slave Interface
18.5.1.2.1. Slave Interface CSR Unit
18.5.1.3. Application Interface Unit
18.5.1.4. Packet FIFO Controller
18.5.1.5. SPRAM
18.5.1.6. MAC
18.5.1.6.1. USB Transactions
18.5.1.6.2. Host Protocol
18.5.1.6.3. Device Protocol
18.5.1.6.4. OTG Protocol
18.5.1.7. Wakeup and Power Control
18.5.1.8. PHY Interface Unit
18.5.1.9. DMA
18.5.2. Local Memory Buffer
18.5.3. Clocks
18.5.3.1. Clock Gating
18.5.4. Resets
18.5.4.1. Reset Requirements
18.5.4.2. Hardware Reset
18.5.4.3. Software Reset
18.5.4.4. Taking the USB 2.0 OTG Controller Out of Reset
18.5.5. Interrupts
18.6. USB OTG Controller Programming Model
18.6.1. Enabling SPRAM ECCs
18.6.2. Host Operation
18.6.2.1. Host Initialization
18.6.2.2. Host Transaction
18.6.3. Device Operation
18.6.3.1. Device Initialization
18.6.3.2. Device Transaction
18.6.3.2.1. IN Transactions
18.6.3.2.2. OUT Transactions
18.6.3.2.3. Control Transfers
18.7. USB 2.0 OTG Controller Address Map and Register Definitions
19. SPI Controller
19.1. Features of the SPI Controller
19.2. SPI Block Diagram and System Integration
19.2.1. SPI Block Diagram
19.3. SPI Controller Signal Description
19.3.1. Interface to HPS I/O
19.3.2. FPGA Routing
19.4. Functional Description of the SPI Controller
19.4.1. Protocol Details and Standards Compliance
19.4.2. SPI Controller Overview
19.4.2.1. Serial Bit-Rate Clocks
19.4.2.1.1. SPI Master Bit-Rate Clock
19.4.2.1.2. SPI Slave Bit-Rate Clock
19.4.2.2. Transmit and Receive FIFO Buffers
19.4.2.3. SPI Interrupts
19.4.3. Transfer Modes
19.4.3.1. Transmit and Receive
19.4.3.2. Transmit Only
19.4.3.3. Receive Only
19.4.3.4. EEPROM Read
19.4.4. SPI Master
19.4.4.1. RXD Sample Delay
19.4.4.2. Data Transfers
19.4.4.3. Master SPI and SSP Serial Transfers
19.4.4.4. Master Microwire Serial Transfers
19.4.5. SPI Slave
19.4.5.1. Slave SPI and SSP Serial Transfers
19.4.5.2. Serial Transfers
19.4.5.3. Glue Logic for Master Port ss_in_n
19.4.6. Partner Connection Interfaces
19.4.6.1. Motorola SPI Protocol
19.4.6.2. Texas Instruments Synchronous Serial Protocol (SSP)
19.4.6.3. National Semiconductor Microwire Protocol
19.4.7. DMA Controller Interface
19.4.8. Slave Interface
19.4.8.1. Control and Status Register Access
19.4.8.2. Data Register Access
19.4.9. Clocks and Resets
19.4.9.1. Clock Gating
19.4.9.2. Taking the SPI Controller Out of Reset
19.5. SPI Programming Model
19.5.1. Master SPI and SSP Serial Transfers
19.5.2. Master Microwire Serial Transfers
19.5.3. Slave SPI and SSP Serial Transfers
19.5.4. Slave Microwire Serial Transfers
19.5.5. Software Control for Slave Selection
19.5.5.1. Example: Slave Selection Software Flow for SPI Master
19.5.5.2. Example: Slave Selection Software Flow for SPI Slave
19.5.6. DMA Controller Operation
19.5.6.1. Transmit FIFO Buffer Underflow
19.5.6.2. Transmit FIFO Watermark
19.5.6.2.1. Example 1: Transmit FIFO Watermark Level = 64
19.5.6.2.2. Example 2: Transmit FIFO Watermark Level = 192
19.5.6.3. Transmit FIFO Buffer Overflow
19.5.6.4. Receive FIFO Buffer Overflow
19.5.6.5. Choosing Receive Watermark Level
19.5.6.6. Receive FIFO Buffer Underflow
19.6. SPI Controller Address Map and Register Definitions
20. I2C Controller
20.1. Features of the I2C Controller
20.2. I2C Controller Block Diagram and System Integration
20.3. I2C Controller Signal Description
20.4. Functional Description of the I2C Controller
20.4.1. Feature Usage
20.4.2. Behavior
20.4.2.1. START and STOP Generation
20.4.2.2. Combined Formats
20.4.3. Protocol Details
20.4.3.1. START and STOP Conditions
20.4.3.2. Addressing Slave Protocol
20.4.3.2.1. 7-Bit Address Format
20.4.3.2.2. 10-Bit Address Format
20.4.3.3. Transmitting and Receiving Protocol
20.4.3.3.1. Master-Transmitter and Slave-Receiver
20.4.3.3.2. Master-Receiver and Slave-Transmitter
20.4.3.4. START BYTE Transfer Protocol
20.4.4. Multiple Master Arbitration
20.4.4.1. Clock Synchronization
20.4.5. Clock Frequency Configuration
20.4.5.1. Minimum High and Low Counts
20.4.5.1.1. Calculating High and Low Counts
20.4.6. SDA Hold Time
20.4.7. DMA Controller Interface
20.4.8. Clocks
20.4.9. Resets
20.4.9.1. Taking the I2C Controller Out of Reset
20.5. I2C Controller Programming Model
20.5.1. Slave Mode Operation
20.5.1.1. Initial Configuration
20.5.1.2. Slave-Transmitter Operation for a Single Byte
20.5.1.3. Slave-Receiver Operation for a Single Byte
20.5.1.4. Slave-Transfer Operation for Bulk Transfers
20.5.1.5. Slave Programming Model
20.5.2. Master Mode Operation
20.5.2.1. Initial Configuration
20.5.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update
20.5.2.3. Master Transmit and Master Receive
20.5.2.4. Master Programming Model
20.5.3. Disabling the I2C Controller
20.5.4. Abort Transfer
20.5.5. DMA Controller Operation
20.5.5.1. Transmit FIFO Underflow
20.5.5.2. Transmit Watermark Level
20.5.5.3. Transmit FIFO Overflow
20.5.5.4. Receive FIFO Overflow
20.5.5.5. Receive Watermark Level
20.5.5.6. Receive FIFO Underflow
20.6. I2C Controller Address Map and Register Definitions
21. UART Controller
21.1. UART Controller Features
21.2. UART Controller Block Diagram and System Integration
21.3. UART Controller Signal Description
21.4. Functional Description of the UART Controller
21.4.1. FIFO Buffer Support
21.4.2. UART(RS232) Serial Protocol
21.4.3. Automatic Flow Control
21.4.3.1. RTC Flow Control Trigger
21.4.3.2. Automatic RTS mode
21.4.3.3. Automatic CTS mode
21.4.4. Clocks
21.4.5. Resets
21.4.5.1. Taking the UART Controller Out of Reset
21.4.6. Interrupts
21.4.6.1. Programmable THRE Interrupt
21.5. DMA Controller Operation
21.5.1. Transmit FIFO Underflow
21.5.2. Transmit Watermark Level
21.5.2.1. IIR_FCR.TET = 1
21.5.2.2. IIR_FCR.TET = 3
21.5.3. Transmit FIFO Overflow
21.5.4. Receive FIFO Overflow
21.5.5. Receive Watermark Level
21.5.6. Receive FIFO Underflow
21.6. UART Controller Address Map and Register Definitions
22. General-Purpose I/O Interface
22.1. Features of the GPIO Interface
22.2. GPIO Interface Block Diagram and System Integration
22.3. GPIO Interface Signal Description
22.4. Functional Description of the GPIO Interface
22.4.1. Debounce Operation
22.4.2. Pin Directions
22.4.3. Taking the GPIO Interface Out of Reset
22.5. GPIO Interface Programming Model
22.6. General-Purpose I/O Interface Address Map and Register Definitions
23. Timers
23.1. Features of the Timers
23.2. Timers Block Diagram and System Integration
23.3. Functional Description of the Timers
23.3.1. Clocks
23.3.2. Resets
23.3.3. Interrupts
23.4. Timers Programming Model
23.4.1. Initialization
23.4.2. Enabling the Timers
23.4.3. Disabling the Timers
23.4.4. Loading the Timers Countdown Value
23.4.5. Servicing Interrupts
23.4.5.1. Clearing the Interrupt
23.4.5.2. Checking the Interrupt Status
23.4.5.3. Masking the Interrupt
23.5. Timers Address Map and Register Definitions
24. Watchdog Timers
24.1. Features of the Watchdog Timers
24.2. Watchdog Timers Block Diagram and System Integration
24.3. Functional Description of the Watchdog Timers
24.3.1. Watchdog Timers Counter
24.3.2. Watchdog Timers Pause Mode
24.3.3. Watchdog Timers Clocks
24.3.4. Watchdog Timers Resets
24.4. Watchdog Timers Programming Model
24.4.1. Setting the Timeout Period Values
24.4.2. Selecting the Output Response Mode
24.4.3. Enabling and Initially Starting a Watchdog Timers
24.4.4. Reloading a Watchdog Counter
24.4.5. Pausing a Watchdog Timers
24.4.6. Disabling and Stopping a Watchdog Timers
24.4.7. Watchdog Timers State Machine
24.5. Watchdog Timers Address Map and Register Definitions
25. CoreSight Debug and Trace
25.1. Features of CoreSight Debug and Trace
25.2. Arm CoreSight Documentation
25.3. CoreSight Debug and Trace Block Diagram and System Integration
25.4. Functional Description of CoreSight Debug and Trace
25.4.1. Debug Access Port
25.4.1.1. JTAG Interface Options
25.4.2. CoreSight SoC-400 Timestamp Generator
25.4.3. System Trace Macrocell
25.4.4. Trace Funnel
25.4.5. CoreSight Trace Memory Controller
25.4.5.1. Embedded Trace FIFO
25.4.5.2. Embedded Trace Router
25.4.5.2.1. Distributed Virtual Memory Support
25.4.6. AMBA Trace Bus Replicator
25.4.7. Trace Port Interface Unit
25.4.8. NoC Trace Ports
25.4.9. Embedded Cross Trigger System
25.4.9.1. Cross Trigger Interface
25.4.9.2. Cross Trigger Matrix
25.4.10. Embedded Trace Macrocell
25.4.11. HPS Debug APB Interface
25.4.12. FPGA Interface
25.4.12.1. DAP
25.4.12.2. STM
25.4.12.3. FPGA-CTI
25.4.12.4. TPIU
25.4.13. Debug Clocks
25.4.14. Debug Resets
25.5. CoreSight Debug and Trace Programming Model
25.5.1. CoreSight Component Address
25.5.2. CTI Trigger Connections to Outside the Debug System
25.5.2.1. CTI
25.5.2.2. FPGA-CTI
25.5.2.3. L3-CTI
25.5.3. Configuring Embedded Cross-Trigger Connections
25.5.3.1. Configuring Trigger Input 0
25.5.3.2. Triggering a Flush of Trace Data to the TPIU
25.5.3.3. Triggering an STM message
25.5.3.4. Triggering a Breakpoint on CPU 1
25.6. CoreSight Debug and Trace Address Map and Register Definitions
A. Booting and Configuration
A.1. FPGA Configuration First Mode
A.1.1. Boot Flow Overview for FPGA Configuration First Mode
A.2. HPS Boot First Mode
A.2.1. Boot Flow Overview for HPS Boot First Mode
A.3. Device Response to External Configuration and Reset Events
B. Accessing the Secure Device Manager Quad SPI Flash Controller through HPS
B.1. Features of the Quad SPI Flash Controller
B.2. Taking Ownership of Quad SPI Controller
B.2.1. Feature Availability under SDM/HPS Ownership of Quad SPI Controller
B.3. Quad SPI Flash Controller Block Diagram and System Integration
B.4. Quad SPI Flash Controller Signal Description
B.5. Functional Description of the Quad SPI Flash Controller
B.5.1. Overview
B.5.2. Data Slave Interface
B.5.2.1. Direct Access Mode
B.5.2.1.1. Data Slave Remapping Example
B.5.2.1.2. AHB
B.5.2.2. Indirect Access Mode
B.5.2.2.1. Indirect Read Operation
B.5.2.2.2. Indirect Write Operation
B.5.2.2.3. Consecutive Reads and Writes
B.5.3. SPI Legacy Mode
B.5.4. Register Slave Interface
B.5.4.1. STIG Operation
B.5.5. Local Memory Buffer
B.5.6. Arbitration between Direct/Indirect Access Controller and STIG
B.5.7. Configuring the Flash Device
B.5.8. XIP Mode
B.5.9. Write Protection
B.5.10. Data Slave Sequential Access Detection
B.5.11. Clocks
B.5.12. Resets
B.5.13. Interrupts
B.6. Quad SPI Flash Controller Programming Model
B.6.1. Setting Up the Quad SPI Flash Controller
B.6.2. Indirect Read Operation
B.6.3. Indirect Write Operation
B.6.4. XIP Mode Operations
B.6.4.1. Entering XIP Mode
B.6.4.1.1. Micron Quad SPI Flash Devices with Support for Basic-XIP
B.6.4.1.2. Micron Quad SPI Flash Devices without Support for Basic-XIP
B.6.4.1.3. Winbond Quad SPI Flash Devices
B.6.4.1.4. Spansion Quad SPI Flash Devices
B.6.4.2. Exiting XIP Mode
B.6.4.3. XIP Mode at Power on Reset
B.7. Accessing the SDM Quad SPI Flash Controller Through HPS Address Map and Register Definitions
C. Operational Status of the HPS to the FPGA Logic
C.1. Overview
C.1.1. SDM Gated Signals
C.1.2. HPS Events
C.1.3. FPGA Events
C.2. Software Requirements
C.2.1. FPGA Boot First Mode
C.2.2. HPS Boot First Mode
C.3. Signal Behavior Event Diagrams
C.3.1. FPGA User Mode Entry
C.3.2. HPS Warm Reset Event
C.3.3. HPS Cold Reset Event
C.3.4. Watchdog Causes HPS Warm Reset Event
C.3.5. Watchdog Causes HPS Cold Reset Event
C.4. SDM Gated Signals