External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide - The Agilex 7 F-Series and I-Series EMIF IP provides external memory interface support for the DDR4 and QDR-IV memory protocols. - 2026-01-26
Version
23.2
Product Type
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Agilex Families > Agilex 7
Device Families > Agilex Families > Agilex 7 > I-Series
Resource Type
Documentation > User Guides
Source Name
DITA
1. About the External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP
1.1. Release Information
2. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – Introduction
2.1. Agilex™ 7 F-Series and I-Series EMIF IP Protocol and Feature Support
2.2. Agilex™ 7 F-Series and I-Series EMIF IP Design Flow
2.3. Agilex™ 7 F-Series and I-Series EMIF IP Design Checklist
3. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – Product Architecture
3.1. Agilex™ 7 F-Series and I-Series EMIF Architecture: Introduction
3.1.1. Agilex™ 7 F-Series and I-Series EMIF Architecture: I/O Subsystem
3.1.2. Agilex™ 7 F-Series and I-Series EMIF Architecture: I/O SSM
3.1.3. Agilex™ 7 F-Series and I-Series EMIF Architecture: I/O Bank
3.1.4. Agilex™ 7 F-Series and I-Series EMIF Architecture: I/O Lane
3.1.4.1. Considerations for Designing DDR4 x72 Interface Together with an AVST x8/x16/x32 Configuration Scheme
3.1.5. Agilex™ 7 F-Series and I-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Agilex™ 7 F-Series and I-Series EMIF Architecture: PHY Clock Tree
3.1.7. Agilex™ 7 F-Series and I-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Agilex™ 7 F-Series and I-Series EMIF Architecture: Clock Phase Alignment
3.2. Agilex™ 7 F-Series and I-Series EMIF Sequencer
3.3. Agilex™ 7 F-Series and I-Series EMIF Calibration
3.3.1. Agilex™ 7 F-Series and I-Series Calibration Stages
3.3.2. Agilex™ 7 F-Series and I-Series Calibration Stages Descriptions
3.3.3. Agilex™ 7 F-Series and I-Series Calibration Flowchart
3.3.4. Agilex™ 7 F-Series and I-Series Calibration Algorithms
3.3.4.1. Calibration Algorithms for DDR4
3.3.4.1.1. DDR4 Read Calibration
3.3.4.1.2. DDR4 Write Calibration
3.3.4.2. Calibration Algorithms for QDR-IV
3.3.4.2.1. QDR-IV Read Calibration
3.3.4.2.2. QDR-IV Write Calibration
3.3.4.3. Guidelines for Debugging Calibration Issues
3.3.4.3.1. Debugging Calibration Failure Using Information from the Calibration report
3.3.4.3.2. Debugging Address and Command Leveling Calibration Failure
3.3.4.3.3. Debugging Address and Command Deskew Failure
3.3.4.3.4. Debugging DQS Enable Failure
3.3.4.3.5. Debugging Read Deskew Calibration Failure
3.3.4.3.6. Debugging VREFIN Calibration Failure
3.3.4.3.7. Debugging LFIFO Calibration Failure
3.3.4.3.8. Debugging Write Leveling Failure
3.3.4.3.9. Debugging Write Deskew Calibration Failure
3.3.4.3.10. Debugging VREFOUT Calibration Failure
3.4. Agilex™ 7 F-Series and I-Series EMIF Controller
3.4.1. Hard Memory Controller
3.4.1.1. Hard Memory Controller Features
3.4.1.2. Hard Memory Controller Main Control Path
3.4.1.3. Data Buffer Controller
3.4.2. Agilex™ 7 F-Series and I-Series Hard Memory Controller Rate Conversion Feature
3.5. User-requested Reset in Agilex™ 7 F-Series and I-Series EMIF IP
3.6. Agilex™ 7 F-Series and I-Series EMIF for Hard Processor Subsystem
3.6.1. Restrictions on I/O Bank Usage for Agilex™ 7 F-Series and I-Series EMIF IP with HPS
3.6.2. Using the Legacy EMIF Debug Toolkit with F-Series and I-Series HPS Interfaces
3.7. Using a Custom Controller with the Hard PHY
3.8. Example of Avalon Memory-Mapped Write/Read Operation
4. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – End-User Signals
4.1. Agilex™ 7 F-Series and I-Series EMIF IP Interface and Signal Descriptions
4.1.1. Agilex™ 7 EMIF IP Interfaces for DDR4
4.1.1.1. local_reset_req for DDR4
4.1.1.2. local_reset_status for DDR4
4.1.1.3. pll_ref_clk for DDR4
4.1.1.4. pll_locked for DDR4
4.1.1.5. ac_parity_err for DDR4
4.1.1.6. oct for DDR4
4.1.1.7. mem for DDR4
4.1.1.8. status for DDR4
4.1.1.9. afi_reset_n for DDR4
4.1.1.10. afi_clk for DDR4
4.1.1.11. afi_half_clk for DDR4
4.1.1.12. afi for DDR4
4.1.1.13. emif_usr_reset_n for DDR4
4.1.1.14. emif_usr_clk for DDR4
4.1.1.15. ctrl_amm for DDR4
4.1.1.16. ctrl_amm_aux for DDR4
4.1.1.17. ctrl_auto_precharge for DDR4
4.1.1.18. ctrl_user_priority for DDR4
4.1.1.19. ctrl_ecc_user_interrupt for DDR4
4.1.1.20. ctrl_ecc_readdataerror for DDR4
4.1.1.21. ctrl_ecc_status for DDR4
4.1.1.22. ctrl_mmr_slave for DDR4
4.1.1.23. hps_emif for DDR4
4.1.1.24. emif_calbus for DDR4
4.1.1.25. emif_calbus_clk for DDR4
4.1.2. Agilex™ 7 EMIF IP Interfaces for QDR-IV
4.1.2.1. local_reset_req for QDR-IV
4.1.2.2. local_reset_status for QDR-IV
4.1.2.3. pll_ref_clk for QDR-IV
4.1.2.4. pll_locked for QDR-IV
4.1.2.5. oct for QDR-IV
4.1.2.6. mem for QDR-IV
4.1.2.7. status for QDR-IV
4.1.2.8. afi_reset_n for QDR-IV
4.1.2.9. afi_clk for QDR-IV
4.1.2.10. afi_half_clk for QDR-IV
4.1.2.11. afi for QDR-IV
4.1.2.12. emif_usr_reset_n for QDR-IV
4.1.2.13. emif_usr_clk for QDR-IV
4.1.2.14. ctrl_amm for QDR-IV
4.1.2.15. emif_calbus for QDR-IV
4.1.2.16. emif_calbus_clk for QDR-IV
4.2. Agilex™ 7 F-Series and I-Series EMIF IP AFI Signals
4.2.1. AFI Clock and Reset Signals
4.2.2. AFI Address and Command Signals
4.2.3. AFI Write Data Signals
4.2.4. AFI Read Data Signals
4.2.5. AFI Calibration Status Signals
4.2.6. AFI Tracking Management Signals
4.2.7. AFI Shadow Register Management Signals
4.3. Agilex™ 7 F-Series and I-Series EMIF IP AFI 4.0 Timing Diagrams
4.3.1. AFI Address and Command Timing Diagrams
4.3.2. AFI Write Sequence Timing Diagrams
4.3.3. AFI Read Sequence Timing Diagrams
4.3.4. AFI Calibration Status Timing Diagram
4.4. Agilex™ 7 F-Series and I-Series EMIF IP Memory Mapped Register (MMR) Tables
4.4.1. ctrlcfg0
4.4.2. ctrlcfg1
4.4.3. dramtiming0
4.4.4. sbcfg1
4.4.5. caltiming0
4.4.6. caltiming1
4.4.7. caltiming2
4.4.8. caltiming3
4.4.9. caltiming4
4.4.10. caltiming9
4.4.11. dramaddrw
4.4.12. sideband0
4.4.13. sideband1
4.4.14. sideband4
4.4.15. sideband6
4.4.16. sideband7
4.4.17. sideband9
4.4.18. sideband11
4.4.19. sideband12
4.4.20. sideband13
4.4.21. sideband14
4.4.22. dramsts
4.4.23. niosreserve0
4.4.24. niosreserve1
4.4.25. sideband16
4.4.26. ecc3: ECC Error and Interrupt Configuration
4.4.27. ecc4: Status and Error Information
4.4.28. ecc5: Address of Most Recent SBE/DBE
4.4.29. ecc6: Address of Most Recent Correction Command Dropped
4.4.30. ecc7: Extension for Address of Most Recent SBE/DBE
4.4.31. ecc8: Extension for Address of Most Recent Correction Command Dropped
5. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – Simulating Memory IP
5.1. Simulation Options
5.2. Simulation Walkthrough
5.2.1. Calibration Modes
5.2.2. Simulation Scripts
5.2.3. Functional Simulation with Verilog HDL
5.2.4. Functional Simulation with VHDL
5.2.5. Simulating the Design Example
5.3. Simulating the Design Example with Mentor Graphics AXI4 Master BFM (Altera FPGA Edition)
5.3.1. Overview of Steps
5.3.2. Generating the EMIF Design Example
5.3.3. Editing the Simulation Design Example with the Platform Designer
5.3.4. Editing the ed_sim.v File
5.3.5. Obtaining the master_test_program.sv File
5.3.6. Running the Simulation
6. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – DDR4 Support
6.1. Agilex™ 7 F-Series and I-Series FPGA EMIF IP Parameter Descriptions
6.1.1. Agilex™ 7 F-Series and I-Series EMIF IP DDR4 Parameters: General
6.1.2. Agilex™ 7 F-Series and I-Series EMIF IP DDR4 Parameters: Memory
6.1.3. Agilex™ 7 F-Series and I-Series EMIF IP DDR4 Parameters: Mem I/O
6.1.4. Agilex™ 7 F-Series and I-Series EMIF IP DDR4 Parameters: FPGA I/O
6.1.5. Agilex™ 7 F-Series and I-Series EMIF IP DDR4 Parameters: Mem Timing
6.1.6. Agilex™ 7 F-Series and I-Series EMIF IP DDR4 Parameters: Controller
6.1.7. Agilex™ 7 F-Series and I-Series EMIF IP DDR4 Parameters: Diagnostics
6.1.8. Agilex™ 7 F-Series and I-Series EMIF IP DDR4 Parameters: Example Designs
6.2. Agilex™ 7 F-Series and I-Series External Memory Interfaces Altera Calibration IP Parameters
6.3. Register Map IP-XACT Support for Agilex™ 7 F-Series and I-Series EMIF DDR4 IP
6.4. Agilex™ 7 F-Series and I-Series FPGA EMIF IP Pin and Resource Planning
6.4.1. Agilex™ 7 F-Series and I-Series FPGA EMIF IP Interface Pins
6.4.1.1. Estimating Pin Requirements
6.4.1.2. DIMM Options
6.4.1.3. Maximum Number of Interfaces
6.4.2. Agilex™ 7 FPGA EMIF IP Resources
6.4.2.1. OCT
6.4.2.2. PLL
6.4.3. Pin Guidelines for Agilex™ 7 F-Series and I-Series FPGA EMIF IP
6.4.3.1. Agilex™ 7 F-Series and I-Series FPGA EMIF IP Banks
6.4.3.2. General Guidelines
6.4.3.3. x4 DIMM Implementation
6.4.3.4. Specific Pin Connection Requirements
6.4.3.5. Command and Address Signals
6.4.3.6. Clock Signals
6.4.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.5. DDR4 Board Design Guidelines
6.5.1. Terminations for DDR4 with Agilex™ 7 F-Series and I-Series Devices
6.5.1.1. Dynamic On-Chip Termination (OCT)
6.5.1.2. Dynamic On-Die Termination (ODT) in DDR4
6.5.1.3. Choosing Terminations on Agilex™ 7 F-Series and I-Series FPGA Devices
6.5.1.4. On-Chip Termination Recommendations for Agilex™ 7 F-Series and I-Series FPGA Devices
6.5.2. Clamshell Topology
6.5.3. General Layout Routing Guidelines
6.5.4. Reference Stackup
6.5.5. Agilex™ 7 F-Series and I-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies
6.5.5.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, LRDIMM, and SODIMM DDR4 Topologies
6.5.5.2. Two DIMMs per Channel (2DPC) for UDIMM, RDIMM, and LRDIMM DDR4 Topologies
6.5.5.3. Two DIMMs per Channel (2DPC) for SODIMM Topology
6.5.5.4. Skew Matching Guidelines for DIMM Configurations
6.5.5.5. Power Delivery Recommendations for the Memory / DIMM Side
6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.5.6.1. Single Rank and Dual Rank x 8 Discrete (Component) Topology
6.5.6.2. Single Rank x 16 and Dual Rank Discrete (Component) Topology
6.5.6.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for DDR4 x 8 and DDR4 x 16 Discrete (Component) Topologies
6.5.6.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.5.6.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.5.7. Agilex™ 7 F-Series and I-Series EMIF Pin Swapping Guidelines
7. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – QDR-IV Support
7.1. Agilex™ 7 FPGA EMIF IP Parameter Descriptions
7.1.1. Agilex™ 7 F-Series and I-Series EMIF IP QDR-IV Parameters: General
7.1.2. Agilex™ 7 F-Series and I-Series EMIF IP QDR-IV Parameters: Memory
7.1.3. Agilex™ 7 F-Series and I-Series EMIF IP QDR-IV Parameters: FPGA I/O
7.1.4. Agilex™ 7 F-Series and I-Series EMIF IP QDR-IV Parameters: Mem Timing
7.1.5. Agilex™ 7 F-Series and I-Series EMIF IP QDR-IV Parameters: Controller
7.1.6. Agilex™ 7 F-Series and I-Series EMIF IP QDR-IV Parameters: Diagnostics
7.1.7. Agilex™ 7 F-Series and I-Series EMIF IP QDR-IV Parameters: Example Designs
6.2. Agilex™ 7 F-Series and I-Series External Memory Interfaces Altera Calibration IP Parameters
7.3. Agilex™ 7 F-Series and I-Series FPGA EMIF IP Pin and Resource Planning
7.3.1. Agilex™ 7 F-Series and I-Series FPGA EMIF IP Interface Pins
7.3.1.1. Estimating Pin Requirements
7.3.1.2. Maximum Number of Interfaces
7.3.2. Agilex™ 7 F-Series and I-Series FPGA EMIF IP Resources
7.3.2.1. OCT
7.3.2.2. PLL
7.3.3. Pin Guidelines for Agilex™ 7 F-Series and I-Series FPGA EMIF IP
7.3.3.1. Agilex™ 7 F-Series and I-Series FPGA EMIF IP Banks
7.3.3.2. General Guidelines
7.3.3.3. QDR IV SRAM Commands and Addresses, AP, and AINV Signals
7.3.3.4. QDR IV SRAM Clock Signals
7.3.3.5. QDR IV SRAM Data, DINV, and QVLD Signals
7.3.3.6. Specific Pin Connection Requirements
7.3.3.7. Resource Sharing Guidelines (Multiple Interfaces)
7.4. QDR-IV Board Design Guidelines
7.4.1. General Layout Routing Guidelines
7.4.2. Reference Stackup
7.4.3. Routing Guidelines for QDR-IV Topology
7.4.3.1. QDR-IV Single Device Memory Topology
7.4.3.2. Skew Matching Guidelines for QDR-IV Configurations
7.4.3.3. Power Delivery Recommendation for QDR-IV Configurations
7.4.4. Agilex™ 7 EMIF Design Guideline Summary
8. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – Timing Closure
8.1. Timing Closure
8.1.1. Timing Analysis
8.1.1.1. PHY or Core
8.2. Optimizing Timing
9. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – I/O Timing Closure
9.1. I/O Timing Closure Overview
9.2. Collateral Generated with Your EMIF IP
9.3. SPICE Decks
9.3.1. Address/Command Simulation Deck
9.3.2. FPGA Write Operation Simulation Deck
9.3.3. FPGA Read Operation Simulation Deck
9.4. File Organization
9.5. Top-level Parameterization File
9.6. IP-Supplied Parameters that You Might Need to Override
9.7. Understanding the *_ip_parameters.dat File and Making a Mask Polygon
9.8. Multi-Rank Topology
9.9. Pin Parasitics
9.10. Mask Evaluation
10. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – Controller Optimization
10.1. Interface Standard
10.2. Bank Management Efficiency
10.3. Data Transfer
10.4. Improving Controller Efficiency
10.4.1. Auto-Precharge Commands
10.4.1.1. Using Auto-precharge to Achieve Highest Memory Bandwidth for DDR4 Interfaces
10.4.2. Additive Latency
10.4.3. Bank Interleaving
10.4.4. Additive Latency and Bank Interleaving
10.4.5. User-Controlled Refresh
10.4.6. Frequency of Operation
10.4.7. Series of Reads or Writes
10.4.8. Data Reordering
10.4.9. Starvation Control
10.4.10. Command Reordering
10.4.11. Bandwidth
10.4.12. Enable Command Priority Control
10.4.13. Controller Pre-pay and Post-pay Refresh (DDR4 Only)
11. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – Debugging
11.1. Interface Configuration Performance Issues
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation
11.2.1. Altera IP Memory Model
11.2.2. Vendor Memory Model
11.2.3. Transcript Window Messages
11.2.4. Modifying the Example Driver to Replicate the Failure
11.3. Timing Issue Characteristics
11.3.1. Evaluating FPGA Timing Issues
11.3.2. Evaluating External Memory Interface Timing Issues
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer
11.4.1. Signals to Monitor with the Signal Tap Logic Analyzer
11.5. Hardware Debugging Guidelines
11.5.1. Create a Simplified Design that Demonstrates the Same Issue
11.5.2. Measure Power Distribution Network
11.5.3. Measure Signal Integrity and Setup and Hold Margin
11.5.4. Vary Voltage
11.5.5. Operate at a Lower Speed
11.5.6. Determine Whether the Issue Exists in Previous Versions of Software
11.5.7. Determine Whether the Issue Exists in the Current Version of Software
11.5.8. Try A Different PCB
11.5.9. Try Other Configurations
11.5.10. Debugging Checklist
11.6. Categorizing Hardware Issues
11.6.1. Signal Integrity Issues
11.6.1.1. Characteristics of Signal Integrity Issues
11.6.1.2. Evaluating Signal Integrity Issues
11.6.1.2.1. Skew
11.6.1.2.2. Crosstalk
11.6.1.2.3. Power System
11.6.1.2.4. Clock Signals
11.6.1.2.5. Address and Command Signals
11.6.1.2.6. Read Data Valid Window and Eye Diagram
11.6.1.2.7. Write Data Valid Window and Eye Diagram
11.6.1.2.8. OCT and ODT Usage
11.6.2. Hardware and Calibration Issues
11.6.2.1. Postamble Timing Issues and Margin
11.6.2.2. Intermittent Issue Evaluation
11.6.2.3. Memory Timing Parameter Evaluation
11.6.2.4. Verify that the Board Has the Correct Memory Component or DIMM Installed
11.7. Debugging with the External Memory Interface Debug Toolkit
11.7.1. Prerequisites for Using the EMIF Debug Toolkit
11.7.2. Configuring a Design to Use the Toolkit
11.7.2.1. Generating a Design Example with the Debug Toolkit
11.7.2.2. Creating a Design Example with Multiple External Memory Interfaces
11.7.2.3. Enabling the EMIF Toolkit in an Existing Design
11.7.3. Launching the EMIF Debug Toolkit
11.7.4. Using the EMIF Debug Toolkit
11.7.4.1. Memory Configuration Tab
11.7.4.2. Calibration Tab
11.7.4.2.1. Rerunning Calibration
11.7.4.2.2. Rerunning the Traffic Generator
3.3.4.3. Guidelines for Debugging Calibration Issues
3.3.4.3.1. Debugging Calibration Failure Using Information from the Calibration report
3.3.4.3.2. Debugging Address and Command Leveling Calibration Failure
3.3.4.3.3. Debugging Address and Command Deskew Failure
3.3.4.3.4. Debugging DQS Enable Failure
3.3.4.3.5. Debugging Read Deskew Calibration Failure
3.3.4.3.6. Debugging VREFIN Calibration Failure
3.3.4.3.7. Debugging LFIFO Calibration Failure
3.3.4.3.8. Debugging Write Leveling Failure
3.3.4.3.9. Debugging Write Deskew Calibration Failure
3.3.4.3.10. Debugging VREFOUT Calibration Failure
11.7.4.4. Calibration Report Tab
11.7.4.5. Calibrate Termination Tab
11.7.4.6. Vref Margining Tab
11.7.4.7. Driver Margining Tab
11.7.4.8. ISSPs Tab
11.7.4.9. Pin Delay Settings Tab
11.7.5. Exporting Tables
11.7.6. Viewing Reports Graphically in the Eye Viewer
11.8. Using the Default Traffic Generator
11.8.1. Reading the Default Traffic Generator Status
11.8.2. Running Infinite Traffic using the Default Traffic Generator
11.8.3. Changing the Reset Trigger of the Default Traffic Generator
11.8.4. Observing Generated Traffic with Signal Tap
11.9. Using the Configurable Traffic Generator (TG2)
11.9.1. Enabling the Traffic Generator in a Design Example
11.9.2. Traffic Generator Block Description
11.9.3. Default Traffic Pattern
11.9.4. Configuration and Status Registers
11.9.5. User Pattern
11.9.5.1. Test Duration / Instruction pattern
11.9.5.2. Address Pattern
11.9.5.2.1. Address Generator Modes
11.9.5.2.2. Address Generator MSB Indices
11.9.5.2.3. Address Generator Effective Width
11.9.5.2.4. Address Generator Relative Frequencies
11.9.5.2.5. Address Pattern Examples - Basic Mode
11.9.5.2.6. Address Pattern Examples - Advanced Mode
11.9.5.3. Data Pattern and Byte Enable
11.9.6. Traffic Generator Status
11.9.7. Starting Traffic with the Traffic Generator
11.9.8. Traffic Generator Configuration User Interface
11.9.8.1. Connecting the Traffic Generator
11.9.8.2. Claiming/Releasing the TG Config Interface
11.9.8.3. Configuring the Traffic Generator
11.9.8.4. Traffic Generator Preset Selection
11.9.8.5. Traffic Generator Status Report
11.9.8.6. Examples of Configuring the TG2 Traffic Generator
11.10. EMIF On-Chip Debug Port
11.10.1. Enabling the On-Chip Debug Port
11.10.2. I/O SSM calbus Bridge Data Structures and Usage
11.10.3. I/O SSM User-RAM Data Structures and Usage
11.10.3.1. Parameter Tables
11.10.3.1.1. Global Parameter Table
11.10.3.1.2. Per-interface Parameter Table Structure
11.10.3.1.3. Parameter Table Arrays
11.10.3.2. Parameter Table Enums
11.10.4. Debug Interface Structure
11.10.4.1. Debug Data Structures
11.10.4.2. Debug Enums
11.10.5. Example: Reading Calibration Results and Margins with the On-Chip Debug Port
11.11. Efficiency Monitor
11.11.1. Enabling the Efficiency Monitor in a Design Example
11.11.2. Efficiency Monitor Block Descriptions
11.11.3. Control and Status Registers
11.11.4. Opening the Efficiency Monitor Toolkit
12. External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide Archives
13. Document Revision History for External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide