MAX 10 JTAG Boundary-Scan Testing User Guide - Describes the boundary-scan cells (BSCs) circuitry architecture and supported JTAG instructions for Intel MAX 10 devices. - 2021-11-01

1. Intel MAX 10 JTAG BST Overview
2. JTAG BST Architecture
2.1. JTAG Pins
2.2. JTAG Circuitry Functional Model
2.3. JTAG Boundary-Scan Register
2.3.1. Boundary-Scan Cells in Intel MAX 10 I/O Pin
3. BST Operation Control
3.1. JTAG IDCODE
3.2. JTAG Secure Mode
3.3. JTAG Private Instruction
3.4. JTAG Instructions
4. I/O Voltage Support in the JTAG Chain
5. Enabling and Disabling JTAG BST Circuitry
6. Guidelines for JTAG BST
7. Boundary-Scan Description Language Support
A. Document Revision History for the Intel MAX 10 JTAG Boundary-Scan Testing User Guide

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