V-Series Transceiver PHY IP Core User Guide - V-Series Transceiver PHY IP Core User Guide - 2025-12-29

1. Introduction to the Protocol-Specific and Native Transceiver PHYs
1.1. Protocol-Specific Transceiver PHYs
1.2. Native Transceiver PHYs
1.3. Non-Protocol-Specific Transceiver PHYs
1.4. Transceiver PHY Modules
1.5. Transceiver Reconfiguration Controller
1.6. Resetting the Transceiver PHY
1.7. Running a Simulation Testbench
1.8. Unsupported Features
2. Getting Started Overview
2.1. Installation and Licensing of IP Cores
2.2. Design Flows
2.3. MegaWizard Plug-In Manager Flow
2.3.1. Specifying Parameters
2.3.2. Simulate the IP Core
3. 10GBASE-R PHY IP Core
3.1. 10GBASE-R PHY Release Information
3.2. 10GBASE-R PHY Device Family Support
3.3. 10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices
3.4. 10GBASE-R PHY Performance and Resource Utilization for Arria V GT Devices
3.5. 10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices
3.6. Parameterizing the 10GBASE-R PHY
3.7. General Option Parameters
3.8. Analog Parameters for Stratix IV Devices
3.9. 10GBASE-R PHY Interfaces
3.10. 10GBASE-R PHY Data Interfaces
3.11. 10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces
3.12. Optional Reset Control and Status Interface
3.13. 10GBASE-R PHY Clocks for Arria V GT Devices
3.14. 10GBASE-R PHY Clocks for Arria V GZ Devices
3.15. 10GBASE-R PHY Clocks for Stratix IV Devices
3.16. 10GBASE-R PHY Clocks for Stratix V Devices
3.17. 10GBASE-R PHY Register Interface and Register Descriptions
3.18. 10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices
3.19. 10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices
3.20. 1588 Delay Requirements
3.21. 10GBASE-R PHY TimeQuest Timing Constraints
3.22. 10GBASE-R PHY Simulation Files and Example Testbench
4. Backplane Ethernet 10GBASE-KR PHY IP Core
4.1. 10GBASE-KR PHY Release Information
4.2. Device Family Support
4.3. 10GBASE-KR PHY Performance and Resource Utilization
4.4. Parameterizing the 10GBASE-KR PHY
4.4.1. 10GBASE-KR Link Training Parameters
4.4.2. 10GBASE-KR Auto-Negotiation and Link Training Parameters
4.4.3. 10GBASE-R Parameters
4.4.4. 1GbE Parameters
4.4.5. Speed Detection Parameters
4.4.6. PHY Analog Parameters
4.5. 10GBASE-KR PHY IP Core Functional Description
4.6. 10GBASE-KR Dynamic Reconfiguration from 1G to 10GbE
4.7. 10GBASE-KR PHY Arbitration Logic Requirements
4.8. 10GBASE-KR PHY State Machine Logic Requirements
4.9. Forward Error Correction (Clause 74)
4.10. 10BASE-KR PHY Interfaces
4.11. 10GBASE-KR PHY Clock and Reset Interfaces
4.11.1. 10GBASE-KR PHY Data Interfaces
4.11.1.1. 10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data
4.11.1.2. 10GBASE-KR PHY Serial Data Interface
4.11.1.3. MII Interface Signals
4.11.2. 10GBASE-KR PHY Control and Status Interfaces
4.11.3. Daisy-Chain Interface Signals
4.11.4. Embedded Processor Interface Signals
4.11.5. Dynamic Reconfiguration Interface Signals
4.12. Register Interface Signals
4.13. 10GBASE-KR PHY Register Definitions
4.14. PMA Registers
4.15. PCS Registers
4.16. Creating a 10GBASE-KR Design
4.17. Editing a 10GBASE-KR MIF File
4.18. Design Example
4.19. SDC Timing Constraints
4.20. Acronyms
5. 1G/10Gbps Ethernet PHY IP Core
5.1. 1G/10GbE PHY Release Information
4.2. Device Family Support
5.3. 1G/10GbE PHY Performance and Resource Utilization
5.4. Parameterizing the 1G/10GbE PHY
4.4.4. 1GbE Parameters
4.4.5. Speed Detection Parameters
4.4.6. PHY Analog Parameters
5.8. 1G/10GbE PHY Interfaces
5.9. 1G/10GbE PHY Clock and Reset Interfaces
5.10. 1G/10GbE PHY Data Interfaces
5.11. XGMII Mapping to Standard SDR XGMII Data
4.11.1.3. MII Interface Signals
5.13. Serial Data Interface
5.14. 1G/10GbE Control and Status Interfaces
4.12. Register Interface Signals
5.16. 1G/10GbE PHY Register Definitions
4.14. PMA Registers
4.15. PCS Registers
5.19. 1G/10GbE GMII PCS Registers
5.20. GIGE PMA Registers
5.21. 1G/10GbE Dynamic Reconfiguration from 1G to 10GbE
5.22. 1G/10GbE PHY Arbitration Logic Requirements
5.23. 1G/10GbE PHY State Machine Logic Requirements
5.24. Editing a 1G/10GbE MIF File
5.25. Creating a 1G/10GbE Design
4.11.5. Dynamic Reconfiguration Interface Signals
4.18. Design Example
5.28. Simulation Support
5.29. TimeQuest Timing Constraints
4.20. Acronyms
6. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
6.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
6.1.1. Features
6.1.2. Release Information
6.1.3. Device Family Support
6.1.4. Resource Utilization
6.2. Using the IP Core
6.2.1. Parameter Settings
6.2.2. Timing Constraints
6.2.3. Changing the PHY's Speed
6.3. Configuration Registers
6.3.1. Register Map
6.3.2. Configuration Registers
6.4. Interface Signals
6.4.1. Clock and Reset Signals
6.4.2. Operating Mode and Speed Signals
6.4.3. GMII Signals
6.4.4. XGMII Signals
6.4.5. Status Signals
6.4.6. Serial Interface Signals
6.4.7. Transceiver Status and Reconfiguration Signals
6.4.8. Avalon Memory-Mapped Interface Signals
7. XAUI PHY IP Core
7.1. XAUI PHY Release Information
7.2. XAUI PHY Device Family Support
7.3. XAUI PHY Performance and Resource Utilization for Stratix IV Devices
7.4. XAUI PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices
7.5. Parameterizing the XAUI PHY
7.6. XAUI PHY General Parameters
7.7. XAUI PHY Analog Parameters
7.8. XAUI PHY Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV Devices
7.9. Advanced Options Parameters
7.10. XAUI PHY Configurations
7.11. XAUI PHY Ports
7.12. XAUI PHY Data Interfaces
7.12.1. SDR XGMII TX Interface
7.12.2. SDR XGMII RX Interface
7.12.3. Transceiver Serial Data Interface
7.13. XAUI PHY Clocks, Reset, and Powerdown Interfaces
7.14. XAUI PHY PMA Channel Controller Interface
7.15. XAUI PHY Optional PMA Control and Status Interface
7.16. XAUI PHY Register Interface and Register Descriptions
7.17. XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX
7.18. XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V Devices
7.18.1. Logical Lane Assignment Restriction
7.18.2. XAUI PHY Dynamic Reconfiguration Interface Signals
4.19. SDC Timing Constraints
7.20. Simulation Files and Example Testbench
8. Interlaken PHY IP Core
8.1. Interlaken PHY Device Family Support
8.2. Parameterizing the Interlaken PHY
8.3. Interlaken PHY General Parameters
8.4. Interlaken PHY Optional Port Parameters
8.5. Interlaken PHY Analog Parameters
8.6. Interlaken PHY Interfaces
8.7. Interlaken PHY Avalon-ST TX Interface
8.8. Interlaken PHY Avalon-ST RX Interface
8.9. Interlaken PHY TX and RX Serial Interface
8.10. Interlaken PHY PLL Interface
8.11. Interlaken Optional Clocks for Deskew
8.12. Interlaken PHY Register Interface and Register Descriptions
8.13. Why Transceiver Dynamic Reconfiguration
8.14. Dynamic Transceiver Reconfiguration Interface
8.15. Interlaken PHY TimeQuest Timing Constraints
8.16. Interlaken PHY Simulation Files and Example Testbench
9. PHY IP Core for PCI Express (PIPE)
9.1. PHY for PCIe (PIPE) Device Family Support
9.2. PHY for PCIe (PIPE) Resource Utilization
9.3. Parameterizing the PHY IP Core for PCI Express (PIPE)
9.4. PHY for PCIe (PIPE) General Options Parameters
9.5. PHY for PCIe (PIPE) Interfaces
9.6. PHY for PCIe (PIPE) Input Data from the PHY MAC
9.7. PHY for PCIe (PIPE) Output Data to the PHY MAC
9.8. PHY for PCIe (PIPE) Clocks
9.9. PHY for PCIe (PIPE) Clock SDC Timing Constraints for Gen3 Designs
9.10. PHY for PCIe (PIPE) Optional Status Interface
9.11. PHY for PCIe (PIPE) Serial Data Interface
9.12. PHY for PCIe (PIPE) Register Interface and Register Descriptions
9.13. PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate
9.13.1. Phase 0
9.13.2. Phase 1
9.13.3. Phase 2 (Optional)
9.13.4. Phase 3 (Optional)
9.13.5. Recommendations for Tuning Link Partner’s Transmitter
9.14. Enabling Dynamic PMA Tuning for PCIe Gen3
9.15. PHY for PCIe (PIPE) Dynamic Reconfiguration
9.15.1. Logical Lane Assignment Restriction
9.16. PHY for PCIe (PIPE) Simulation Files and Example Testbench
10. Custom PHY IP Core
10.1. Device Family Support
10.2. Performance and Resource Utilization
10.3. Parameterizing the Custom PHY
10.3.1. General Options Parameters
10.3.2. Word Alignment Parameters
10.3.3. Rate Match FIFO Parameters
10.3.4. 8B/10B Encoder and Decoder Parameters
10.3.5. Byte Order Parameters
10.3.6. PLL Reconfiguration Parameters
10.3.7. Analog Parameters
10.3.8. Presets for Ethernet
10.4. Interfaces
10.4.1. Data Interfaces
10.4.2. Clock Interface
10.4.3. Optional Status Interface
3.12. Optional Reset Control and Status Interface
10.4.5. Register Interface and Register Descriptions
10.4.6. Custom PHY IP Core Registers
10.4.6.1. PMA Common Control and Status Registers
10.4.6.2. Reset Control Registers–Automatic Reset Controller
10.4.6.3. Reset Controls –Manual Mode
10.4.6.4. PMA Control and Status Registers
10.4.6.5. Custom PCS
4.19. SDC Timing Constraints
10.4.8. Dynamic Reconfiguration
11. Low Latency PHY IP Core
11.1. Device Family Support
11.2. Performance and Resource Utilization
11.3. Parameterizing the Low Latency PHY
11.4. General Options Parameters
11.5. Additional Options Parameters
11.6. PLL Reconfiguration Parameters
11.7. Low Latency PHY Analog Parameters
11.8. Low Latency PHY Interfaces
11.9. Low Latency PHY Data Interfaces
11.10. Optional Status Interface
11.11. Low Latency PHY Clock Interface
11.12. Optional Reset Control and Status Interface
11.13. Register Interface and Register Descriptions
11.14. Dynamic Reconfiguration
4.19. SDC Timing Constraints
11.16. Simulation Files and Example Testbench
12. Deterministic Latency PHY IP Core
12.1. Deterministic Latency Auto-Negotiation
12.2. Achieving Deterministic Latency
12.3. Deterministic Latency PHY Delay Estimation Logic
12.4. Deterministic Latency PHY Device Family Support
12.5. Parameterizing the Deterministic Latency PHY
12.5.1. General Options Parameters for Deterministic Latency PHY
12.5.2. Additional Options Parameters for Deterministic Latency PHY
12.5.3. PLL Reconfiguration Parameters for Deterministic Latency PHY
12.5.4. Deterministic Latency PHY Analog Parameters
12.6. Interfaces for Deterministic Latency PHY
12.7. Data Interfaces for Deterministic Latency PHY
12.8. Clock Interface for Deterministic Latency PHY
12.9. Optional TX and RX Status Interface for Deterministic Latency PHY
12.10. Optional Reset Control and Status Interfaces for Deterministic Latency PHY
12.11. Register Interface and Descriptions for Deterministic Latency PHY
12.12. Dynamic Reconfiguration for Deterministic Latency PHY
12.13. Channel Placement and Utilization for Deterministic Latency PHY
4.19. SDC Timing Constraints
12.15. Simulation Files and Example Testbench for Deterministic Latency PHY
13. Stratix V Transceiver Native PHY IP Core
13.1. Device Family Support for Stratix V Native PHY
13.2. Performance and Resource Utilization for Stratix V Native PHY
13.3. Parameter Presets
13.4. Parameterizing the Stratix V Native PHY
13.4.1. General Parameters for Stratix V Native PHY
13.4.2. PMA Parameters for Stratix V Native PHY
13.4.3. Standard PCS Parameters for the Native PHY
13.4.3.1. Standard PCS Pattern Generators
13.4.4. 10G PCS Parameters for Stratix V Native PHY
13.4.4.1. 10G PCS Pattern Generators
13.5. Interfaces for Stratix V Native PHY
13.5.1. Common Interface Ports for Stratix V Native PHY
13.5.2. Standard PCS Interface Ports
13.5.3. 10G PCS Interface
13.6. ×6/×N Bonded Clocking
13.7. xN Non-Bonded Clocking
13.8. SDC Timing Constraints of Stratix V Native PHY
13.9. Dynamic Reconfiguration for Stratix V Native PHY
13.10. Simulation Support
13.11. Slew Rate Settings
14. Arria V Transceiver Native PHY IP Core
14.1. Device Family Support
14.2. Performance and Resource Utilization
14.3. Parameterizing the Arria V Native PHY
14.4. General Parameters
14.5. PMA Parameters
14.5.1. TX PMA Parameters
14.5.2. TX PLL Parameters
14.5.3. RX PMA Parameters
14.6. Standard PCS Parameters
14.6.1. Phase Compensation FIFO
14.6.2. Byte Ordering Block Parameters
14.6.3. Byte Serializer and Deserializer
14.6.4. 8B/10B
14.6.5. Rate Match FIFO
14.6.6. Word Aligner and BitSlip Parameters
14.6.7. Bit Reversal and Polarity Inversion
14.7. Interfaces
14.7.1. Common Interface Ports
13.5.2. Standard PCS Interface Ports
14.8. SDC Timing Constraints
14.9. Dynamic Reconfiguration
14.10. Simulation Support
14.11. Slew Rate Settings
15. Arria V GZ Transceiver Native PHY IP Core
15.1. Device Family Support for Arria V GZ Native PHY
15.2. Performance and Resource Utilization for Arria V GZ Native PHY
13.3. Parameter Presets
15.4. Parameterizing the Arria V GZ Native PHY
15.4.1. General Parameters for Arria V GZ Native PHY
15.4.2. PMA Parameters for Arria V GZ Native PHY
13.4.3. Standard PCS Parameters for the Native PHY
13.4.3.1. Standard PCS Pattern Generators
15.4.4. 10G PCS Parameters for Arria V GZ Native PHY
13.4.4.1. 10G PCS Pattern Generators
15.5. Interfaces for Arria V GZ Native PHY
15.5.1. Common Interface Ports for Arria V GZ Native PHY
15.5.2. Standard PCS Interface Ports
15.5.3. 10G PCS Interface
15.6. SDC Timing Constraints of Arria V GZ Native PHY
15.7. Dynamic Reconfiguration for Arria V GZ Native PHY
15.8. Simulation Support
15.9. Slew Rate Settings
16. Cyclone V Transceiver Native PHY IP Core Overview
16.1. Cyclone Device Family Support
16.2. Cyclone V Native PHY Performance and Resource Utilization
16.3. Parameterizing the Cyclone V Native PHY
16.4. General Parameters
16.5. PMA Parameters
16.5.1. TX PMA Parameters
14.5.2. TX PLL Parameters
16.5.3. RX PMA Parameters
16.6. Standard PCS Parameters
16.6.1. Phase Compensation FIFO
16.6.2. Byte Ordering Block Parameters
16.6.3. Byte Serializer and Deserializer
16.6.4. 8B/10B
16.6.5. Rate Match FIFO
16.6.6. Word Aligner and BitSlip Parameters
14.6.7. Bit Reversal and Polarity Inversion
14.7. Interfaces
16.7.1. Common Interface Ports
16.7.2. Cyclone V Standard PCS Interface Ports
16.8. SDC Timing Constraints
16.9. Dynamic Reconfiguration
16.10. Simulation Support
16.11. Slew Rate Settings
17. Transceiver Reconfiguration Controller IP Core Overview
17.1. Transceiver Reconfiguration Controller System Overview
17.2. Transceiver Reconfiguration Controller Performance and Resource Utilization
17.3. Parameterizing the Transceiver Reconfiguration Controller IP Core
17.4. Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys
17.4.1. General Options Parameters
17.5. Transceiver Reconfiguration Controller Interfaces
17.5.1. MIF Reconfiguration Management Avalon-MM Master Interface
17.5.2. Transceiver Reconfiguration Interface
17.5.3. Reconfiguration Management Interface
17.6. Transceiver Reconfiguration Controller Memory Map
17.7. Transceiver Reconfiguration Controller Calibration Functions
17.7.1. Offset Cancellation
17.7.2. Duty Cycle Calibration
17.7.3. Auxiliary Transmit (ATX) PLL Calibration
17.8. Transceiver Reconfiguration Controller PMA Analog Control Registers
17.9. Transceiver Reconfiguration Controller Eye Viewer Registers
17.9.1. Eye Viewer Usage Example
17.10. Transceiver Reconfiguration Controller DFE Registers
17.11. Controlling DFE Using Register-Based Reconfiguration
17.11.1. Turning on DFE Continuous Adaptive mode
17.11.2. Turning on Triggered DFE Mode
17.11.3. Setting the First Tap Value Using DFE in Manual Mode
17.12. Transceiver Reconfiguration Controller AEQ Registers
17.13. Transceiver Reconfiguration Controller ATX PLL Calibration Registers
17.14. Transceiver Reconfiguration Controller PLL Reconfiguration
17.15. Transceiver Reconfiguration Controller PLL Reconfiguration Registers
17.16. Transceiver Reconfiguration Controller DCD Calibration Registers
17.17. Transceiver Reconfiguration Controller Channel and PLL Reconfiguration
17.17.1. Channel Reconfiguration
17.17.2. PLL Reconfiguration
17.18. Transceiver Reconfiguration Controller Streamer Module Registers
17.18.1. Mode 0 Streaming a MIF for Reconfiguration
17.18.2. Mode 1 Avalon-MM Direct Writes for Reconfiguration
17.19. MIF Generation
17.20. Creating MIFs for Designs that Include Bonded or GT Channels
17.21. MIF Format
17.22. xcvr_diffmifgen Utility
17.23. Reduced MIF Creation
17.24. Changing Transceiver Settings Using Register-Based Reconfiguration
17.24.1. Register-Based Write
17.24.2. Register-Based Read
17.25. Changing Transceiver Settings Using Streamer-Based Reconfiguration
17.25.1. Direct Write Reconfiguration
17.25.2. Streamer-Based Reconfiguration
17.26. Pattern Generators for the Stratix V and Arria V GZ Native PHYs
17.26.1. Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration
17.26.2. Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration
17.26.3. Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based Reconfiguration
17.26.4. Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based Reconfiguration
17.27. Understanding Logical Channel Numbering
17.27.1. Two PHY IP Core Instances Each with Four Bonded Channels
17.27.2. One PHY IP Core Instance with Eight Bonded Channels
17.28. Two PHY IP Core Instances Each with Non-Bonded Channels
17.29. Transceiver Reconfiguration Controller to PHY IP Connectivity
17.30. Merging TX PLLs In Multiple Transceiver PHY Instances
17.31. Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs
17.32. Loopback Modes
18. Transceiver PHY Reset Controller IP Core
18.1. Device Family Support for Transceiver PHY Reset Controller
18.2. Performance and Resource Utilization for Transceiver PHY Reset Controller
18.3. Parameterizing the Transceiver PHY Reset Controller IP
18.4. Transceiver PHY Reset Controller Parameters
18.5. Transceiver PHY Reset Controller Interfaces
18.6. Timing Constraints for Bonded PCS and PMA Channels
19. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices
19.1. Parameterizing the Transceiver PLL PHY
19.2. Transceiver PLL Parameters
19.3. Transceiver PLL Signals
20. Analog Parameters Set Using QSF Assignments
20.1. Making QSF Assignments Using the Assignment Editor
20.2. Analog Settings for Arria V Devices
20.2.1. Analog Settings for Arria V Devices
20.2.1.1. XCVR_IO_PIN_TERMINATION
20.2.1.2. XCVR_REFCLK_PIN_TERMINATION
20.2.1.3. XCVR_TX_SLEW_RATE_CTRL
20.2.1.4. XCVR_VCCR_ VCCT_VOLTAGE
20.2.2. Analog Settings Having Global or Computed Values for Arria V Devices
20.2.2.1. CDR_BANDWIDTH_PRESET
20.2.2.2. PLL_BANDWIDTH_PRESET
20.2.2.3. XCVR_RX_DC_GAIN
20.2.2.4. XCVR_ANALOG_SETTINGS_PROTOCOL
20.2.2.5. XCVR_RX_COMMON_MODE_VOLTAGE
20.2.2.6. XCVR_RX_LINEAR_EQUALIZER_CONTROL
20.2.2.7. XCVR_RX_SD_ENABLE
20.2.2.8. XCVR_RX_SD_OFF
20.2.2.9. XCVR_RX_SD_ON
20.2.2.10. XCVR_RX_SD_THRESHOLD
20.2.2.11. XCVR_TX_COMMON_MODE_VOLTAGE
20.2.2.12. XCVR_TX_PRE_EMP_1ST_POST_TAP
20.2.2.13. XCVR_TX_RX_DET_ENABLE
20.2.2.14. XCVR_TX_RX_DET_MODE
20.2.2.15. XCVR_TX_VOD
20.2.2.16. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.3. Analog Settings for Arria V GZ Devices
20.3.1. Analog Settings for Arria V GZ Devices
20.2.1.1. XCVR_IO_PIN_TERMINATION
20.2.1.2. XCVR_REFCLK_PIN_TERMINATION
20.3.1.3. XCVR_RX_BYPASS_EQ_STAGES_234
20.2.1.3. XCVR_TX_SLEW_RATE_CTRL
20.3.1.5. XCVR_VCCA_VOLTAGE
20.3.1.6. XCVR_VCCR_VCCT_VOLTAGE
20.3.2. Analog Settings Having Global or Computed Default Values for Arria V GZ Devices
20.2.2.1. CDR_BANDWIDTH_PRESET
20.3.2.2. master_ch_number
20.2.2.2. PLL_BANDWIDTH_PRESET
20.3.2.4. reserved_channel
20.3.2.5. XCVR_ANALOG_SETTINGS_PROTOCOL
20.3.2.6. XCVR_RX_DC_GAIN
20.3.2.7. XCVR_RX_LINEAR_EQUALIZER_CONTROL
20.3.2.8. XCVR_RX_COMMON_MODE_VOLTAGE
20.3.2.9. XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
20.2.2.7. XCVR_RX_SD_ENABLE
20.3.2.11. XCVR_RX_SD_OFF
20.3.2.12. XCVR_RX_SD_ON
20.3.2.13. XCVR_RX_SD_THRESHOLD
20.3.2.14. XCVR_TX_COMMON_MODE_VOLTAGE
20.3.2.15. XCVR_TX_PRE_EMP_PRE_TAP_USER
20.3.2.16. XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
20.3.2.17. XCVR_TX_PRE_EMP_1ST_POST_TAP
20.3.2.18. XCVR_TX_PRE_EMP_2ND_POST_TAP
20.3.2.19. XCVR_TX_PRE_EMP_INV_2ND_TAP
20.3.2.20. XCVR_TX_PRE_EMP_INV_PRE_TAP
20.3.2.21. XCVR_TX_PRE_EMP_PRE_TAP
20.2.2.13. XCVR_TX_RX_DET_ENABLE
20.2.2.14. XCVR_TX_RX_DET_MODE
20.3.2.24. XCVR_TX_RX_DET_OUTPUT_SEL
20.3.2.25. XCVR_TX_VOD
20.2.2.16. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.4. Analog Settings for Cyclone V Devices
20.2.1.1. XCVR_IO_PIN_TERMINATION
20.2.1.2. XCVR_REFCLK_PIN_TERMINATION
20.2.1.3. XCVR_TX_SLEW_RATE_CTRL
20.2.1.4. XCVR_VCCR_ VCCT_VOLTAGE
20.4.5. Analog Settings Having Global or Computed Values for Cyclone V Devices
20.2.2.1. CDR_BANDWIDTH_PRESET
20.2.2.2. PLL_BANDWIDTH_PRESET
20.4.5.3. XCVR_ANALOG_SETTINGS_PROTOCOL
20.4.5.4. XCVR_RX_DC_GAIN
20.2.2.6. XCVR_RX_LINEAR_EQUALIZER_CONTROL
20.2.2.5. XCVR_RX_COMMON_MODE_VOLTAGE
20.2.2.7. XCVR_RX_SD_ENABLE
20.2.2.8. XCVR_RX_SD_OFF
20.2.2.9. XCVR_RX_SD_ON
20.4.5.10. XCVR_RX_SD_THRESHOLD
20.2.2.11. XCVR_TX_COMMON_MODE_VOLTAGE
20.4.5.12. XCVR_TX_PRE_EMP_1ST_POST_TAP
20.2.2.13. XCVR_TX_RX_DET_ENABLE
20.2.2.14. XCVR_TX_RX_DET_MODE
20.2.2.15. XCVR_TX_VOD
20.2.2.16. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
20.5. Analog Settings for Stratix V Devices
20.5.1. Analog PCB Settings for Stratix V Devices
20.5.1.1. XCVR_GT_IO_PIN_TERMINATION
20.2.1.1. XCVR_IO_PIN_TERMINATION
20.2.1.2. XCVR_REFCLK_PIN_TERMINATION
20.3.1.3. XCVR_RX_BYPASS_EQ_STAGES_234
20.2.1.3. XCVR_TX_SLEW_RATE_CTRL
20.3.1.5. XCVR_VCCA_VOLTAGE
20.5.1.7. XCVR_VCCR_VCCT_VOLTAGE
20.5.2. Analog Settings Having Global or Computed Default Values for Stratix V Devices
20.2.2.1. CDR_BANDWIDTH_PRESET
20.5.2.2. master_ch_number
20.2.2.2. PLL_BANDWIDTH_PRESET
20.5.2.4. reserved_channel
20.3.2.5. XCVR_ANALOG_SETTINGS_PROTOCOL
20.5.2.6. XCVR_GT_RX_DC_GAIN
20.3.2.6. XCVR_RX_DC_GAIN
20.3.2.7. XCVR_RX_LINEAR_EQUALIZER_CONTROL
20.5.2.9. XCVR_GT_RX_COMMON_ MODE_VOLTAGE
20.5.2.10. XCVR_GT_RX_CTLE
20.5.2.11. XCVR_GT_TX_COMMON_ MODE_VOLTAGE
20.5.2.12. XCVR_GT_TX_PRE_EMP_1ST_POST_TAP
20.5.2.13. XCVR_GT_TX_PRE_EMP_ INV_PRE_TAP
20.5.2.14. XCVR_GT_TX_PRE_EMP_ PRE_TAP
20.5.2.15. XCVR_GT_TX_VOD_MAIN_TAP
20.3.2.8. XCVR_RX_COMMON_MODE_VOLTAGE
20.3.2.9. XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
20.2.2.7. XCVR_RX_SD_ENABLE
20.3.2.11. XCVR_RX_SD_OFF
20.3.2.12. XCVR_RX_SD_ON
20.3.2.13. XCVR_RX_SD_THRESHOLD
20.3.2.14. XCVR_TX_COMMON_MODE_VOLTAGE
20.3.2.15. XCVR_TX_PRE_EMP_PRE_TAP_USER
20.3.2.16. XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
20.5.2.25. XCVR_TX_PRE_EMP_1ST_POST_TAP
20.5.2.26. XCVR_TX_PRE_EMP_2ND_POST_TAP
20.3.2.19. XCVR_TX_PRE_EMP_INV_2ND_TAP
20.3.2.20. XCVR_TX_PRE_EMP_INV_PRE_TAP
20.5.2.29. XCVR_TX_PRE_EMP_PRE_TAP
20.2.2.13. XCVR_TX_RX_DET_ENABLE
20.2.2.14. XCVR_TX_RX_DET_MODE
20.3.2.24. XCVR_TX_RX_DET_OUTPUT_SEL
20.5.2.33. XCVR_TX_VOD
20.2.2.16. XCVR_TX_VOD_PRE_EMP_CTRL_SRC
21. Migrating from Stratix IV to Stratix V Devices Overview
21.1. Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers
21.2. Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices
21.3. Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices
21.4. Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices
21.5. Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V Devices
21.6. Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices
21.7. Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices
22. Additional Information for the Transceiver PHY IP Core
22.1. Revision History for the Transceiver PHY IP Core User Guide
22.2. How to Contact Intel

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