6.3. Construct Well-Formed Loops - A well-formed loop has an exit condition that compares against an integer bound and has a simple induction increment of one per iteration. The Intel HLS Compiler Pro Edition can analyze well-formed loops efficiently, which can help improve the performance of your component. - 2025-12-16

Altera High Level Synthesis Compiler Pro Edition Best Practices Guide

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A well-formed loop has an exit condition that compares against an integer bound and has a simple induction increment of one per iteration. The Intel® HLS Compiler Pro Edition can analyze well-formed loops efficiently, which can help improve the performance of your component.

The following example is a well-formed loop:
for(int i=0; i < N; i++)
{
    //statements
}

Well-formed nested loops can also help maximize the performance of your component.

The following example is a well-formed nested loop structure:
for(int i=0; i < N; i++)
{
   //statements
   for(int j=0; j < M; j++)
   {
      //statements
   }
}