Quartus® Prime Pro Edition User Guide - Describes timing and logic constraints that influence how the Compiler implements your design, such as pin assignments, device options, logic options, and timing constraints. Use the Interface Planner to prototype interface implementations, plan clocks, and quickly define a legal device floorplan. Use the Pin Planner to visualize, modify, and validate all I/O assignments in a graphical representation of the target device. - 2025-07-07

Version

25.1.1

Product Type

Device Families > Agilex Families > Agilex 5

Device Families > Agilex Families > Agilex 5 > E-Series

Device Families > Agilex Families

Device Families > Agilex Families > Agilex 7

Device Families > Agilex Families > Agilex 3

Device Families > Stratix Families

Device Families > Agilex Families > Agilex 7 > I-Series

Device Families > Cyclone Families > Cyclone 10 > Cyclone 10 GX

Device Families > Cyclone Families > Cyclone 10

Device Families > Agilex Families > Agilex 5 > D-Series

Device Families > Agilex Families > Agilex 7 > M-Series

Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition

Device Families > Arria Families > Arria 10

Device Families > Agilex Families > Agilex 7 > F-Series

Device Families > Stratix Families > Stratix 10

Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software

Device Families > Cyclone Families

Device Families > Arria Families

Device Families > Agilex Families > Agilex 3 > C-Series

Resource Type

Documentation > User Guides

Source Name

DITA