3.2. Assigning I/O Pins - Use the Pin Planner to visualize, modify, and validate I/O assignments in a graphical representation of the target device. - 2025-12-16

Quartus Prime Pro Edition User Guide Design Constraints
Version
25.1.1
Use the Pin Planner to visualize, modify, and validate I/O assignments in a graphical representation of the target device.
You can increase the accuracy of I/O assignment analysis by reserving specific device pins to accommodate undefined but expected I/O.
Note: You must assign all I/Os in your design before you can generate a .sof file for programming the target device. Starting in Quartus® Prime Pro Edition version 25.1.1, the Assembler does not generate a .sof programming file during compilation unless all I/Os have location and I/O standard assignments. Previously, Quartus® Prime Pro Edition only issued a critical warning during the Fitter stage if a design lacks complete pin location and I/O standard assignments but still allowed .sof generation.

To assign I/O pins in the Pin Planner, follow these steps:

  1. Open an Quartus® Prime project, and then click Assignments > Pin Planner.
  2. Click Processing > Start Analysis & Elaboration to elaborate the design and display All Pins in the device view.
  3. To locate or highlight pins for assignment, click Pin Finder or a pin type under Highlight Pins in the Tasks pane.
  4. (Optional) To define a custom group of nodes for assignment, select one or more nodes in the Groups or All Pins list, and click Create Group.
  5. Enter assignments of logic, I/O standards, interface IP, and properties for device I/O pins in the All Pins spreadsheet, or by dragging into the package view.
  6. To assign properties to differential pin pairs, click Show Differential Pin Pair Connections. A red connection line appears between positive (p) and negative (n) differential pins.
  7. (Optional) To create board trace model assignments:
    1. Right-click an output or bidirectional pin, and click Board Trace Model. For differential I/O standards, the board trace model uses a differential pin pair with two symmetrical board trace models.
    2. Specify board trace parameters on the positive end of the differential pin pair. The assignment applies to the corresponding value on the negative end of the differential pin pair.
  8. To run a full I/O assignment analysis, click Run I/O Assignment Analysis. The Fitter reports analysis results. Only reserved pins are analyzed prior to design synthesis.