Some Altera® FPGA devices support assignments to I/O banks. I/O banks are a logical grouping of I/O pins for convenience in making certain types of assignments, such as I/O standard assignments.
When targeting a device family that supports I/O bank assignments, the I/O
Bank cell value automatically populates in Pin Planner once you select
a corresponding pin Location. The rows for
various I/O banks
are color coded for easy
visual
identification.
Figure 63. Pin Location and I/O Bank Cells in Pin Planner
When you save your Pin Planner constraints, the pin location saves to the project .qsf that also saves the I/O bank locations as a comment. Command-line users can use this comment to identify I/O bank locations for the placed pins without launching the Quartus® Prime software GUI.
Figure 64. I/O Bank Location Saved As Comment in QSF