Figure 13. Single Data Rate Input Register
| Command | Command Example | Description |
|---|---|---|
| create_clock | create_clock -name sdr_in_clk -period "100 MHz" sdr_in_clk | Creates clock setting for the input clock. |
| set_input_delay | set_input_delay -clock sdr_in_clk 0.15 sdr_in_data | Instructs the Timing Analyzer to analyze the timing of the input I/O with a 0.15 ns input delay. |