1.7. Register Packing - The GPIO IP allows you to pack registers into the periphery to save area and resource utilization. - 2025-12-18

GPIO IP User Guide Arria 10 and Cyclone 10 GX Devices

Version
25.3
The GPIO IP allows you to pack registers into the periphery to save area and resource utilization.

You can configure the full-rate DDIO on the input and output path as a flip flop by adding .qsf assignments.

Table 12.  Register Packing .qsf Assignments
Path .qsf Assignment
Input register packing set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register>
Output register packing set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register>
Output enable register packing set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to register>
Note: The .qsf assignments do not guarantee register packing. However, these assignments enable the Fitter to find a legal placement. Otherwise, the Fitter keeps the flip flop in the core. When you set the Output Enable Register Packing to ON, you must set the Output Register Packing to ON.