5.4. Optional Features - The SDI II IP core also provides some optional features. - 2025-12-15

SDI II IP User Guide

Version: 24.1

1. SDI II Intel FPGA IP Quick Reference
2. SDI II IP Core Overview
2.1. Release Information
2.2. Device Family Support
2.3. General Description
2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started
3.1. Installing and Licensing Intel FPGA IP Cores
3.1.1. Intel FPGA IP Evaluation Mode
3.2. Design Walkthrough
3.2.1. Creating a New Quartus Prime Project
3.2.2. Launching IP Catalog
3.2.3. Parameterizing the IP Core
3.2.4. Generating a Design Example and Simulation Testbench
3.3. SDI II IP Core Component Files
3.4. Compiling the SDI II IP Core Design
3.5. Programming an FPGA
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
5.1. Protocol
5.1.1. Transmitter
5.1.2. Receiver
5.2. Transceiver
5.3. Submodules
5.3.1. Insert Line
5.3.2. Insert/Check CRC
5.3.3. Insert Payload ID
5.3.4. Match TRS
5.3.5. Scrambler
5.3.6. TX Sample
5.3.7. Clock Enable Generator
5.3.8. RX Sample
5.3.9. Detect Video Standard
5.3.10. Detect 1 and 1/1.001 Rates
5.3.11. Transceiver Controller
5.3.12. Descrambler
5.3.13. TRS Aligner
5.3.14. 3Gb Demux
5.3.15. Extract Line
5.3.16. Extract Payload ID
5.3.17. Detect Format
5.3.18. Sync Streams
5.3.19. Convert SD Bits
5.3.20. Insert Sync Bits
5.3.21. Remove Sync Bits
5.4. Optional Features
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion
5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion
5.4.3. SMPTE RP168 Switching Support
5.4.4. SD 20-Bit Interface for Dual/Triple Rate
5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices
5.4.6. Intel FPGA Video Streaming Interface
5.4.6.1. RGB Pixel Packing
5.4.6.2. YCbCr 444 Pixel Packing
5.4.6.3. YCbCr 422 Pixel Packing
5.4.6.4. Supported Modes
6. SDI II IP Core Signals
6.1. SDI II IP Core Resets and Clocks
6.2. Transmitter Protocol Signals
6.2.1. Image Mapping
6.3. Receiver Protocol Signals
6.3.1. rx_format
6.4. Transceiver Signals
6.5. Transmitter Streaming Video and Control Signals
6.6. Receiver Streaming Video and Control Signals
7. SDI II IP Core Design Considerations
7.1. Transceiver Handling Guidelines
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices
7.1.1.1. Modifying the Transceiver Reconfiguration Controller
7.1.1.2. Modifying the Reconfiguration Management
7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Arria 10, Cyclone 10 GX, and Stratix 10 Devices
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core
7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel
7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates
7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel
7.1.2.5. Potential Routing Problem During Fitter Stage in Arria 10 and Cyclone 10 GX Devices
7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Arria 10 and Cyclone 10 GX Devices
7.1.2.7. Unused Transceiver Channels
7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Stratix 10 Devices
7.1.3. Handling Transceiver in Agilex™ 7 F-Tile Devices
7.1.3.1. System PLL Clocking Mode
7.1.3.2. RX Transceiver Settings
7.1.3.2.1. Multi-rate Designs
7.1.3.2.2. Triple-rate Designs
7.1.3.2.3. Single-rate Designs
7.1.3.3. TX Transceiver Settings
7.1.3.4. Unused Transceiver Tiles
7.1.3.5. SmartVID Settings
7.1.3.6. Dynamic Reconfiguration
7.1.3.7. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.2. Timing Violation
7.3. SDI II IP Core Registers
7.3.1. SDI II Tx Register Summary
7.3.2. SDI II Tx Register Description
7.3.3. SDI II Rx Register Summary
7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples
8.1. Design Examples for Arria 10, Cyclone 10 GX, Stratix 10, and Agilex™ 7 F-Tile Devices
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.2.1. Design Example Components
8.2.1.1. Video Pattern Generator
8.2.1.2. Transceiver Reconfiguration Controller
8.2.1.3. Reconfiguration Management
8.2.1.4. Reconfiguration Router
8.2.1.5. Avalon Memory-Mapped Interface Translators
8.2.2. Design Reference
8.2.2.1. Video Pattern Generator Signals
8.2.2.2. Transceiver Reconfiguration Controller Signals
8.2.2.3. Reconfiguration Management Parameters
8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design
8.2.3.1. Simulation Run Time
9. SDI II Intel FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel FPGA IP User Guide

The SDI II IP core also provides some optional features.

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