AN 766: Intel Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline - This is a high speed signal interface design guideline for Stratix 10 devices. - 2019-03-12

Intel Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel Stratix 10 Devices and Transceiver Channels
PCB Stackup Selection Guideline
Recommendations for High Speed Signal PCB Routing
FPGA Fan-out Region Design
Signal Break-out Recommendations
Option 1: Via-In-Pad Topology
Option 2: Dog-bone with GND Cutout at BGA Pad Topology
Option 3: Micro-via Topology
GND Cutout Under BGA Pads in Fan-out Configuration
Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations
Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations
Comparison of Conventional and Recommended Break-out Routing Topologies
Conventional Jog-out Routings with Skew-matching Right After Break-out
Performance Comparison Between Case 1 and Case 3
Performance Comparison Between Case 2 and Case 4
Performance Comparison Between Case 1 and Case 5
Performance Comparison Between Case 2 and Case 6
The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines
0201 AC Capacitor
Sweeping Anti-pad Radius
Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor
Sweeping Anti-pad Radius
Sweeping Void Width Only on the First GND Plane under the Capacitor
Adding a Trace Reference to the 0201 AC Capacitor
Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline
CFP2 Host Connector, Module Assembly, and Pinout
CFP4 Host Connector, Module Assembly, and Pinout
Recommended PCB Design Guideline at the CFP2/CFP4 Connector
CFP4 Design Example and Optimization Performance
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization
Two Different Break-out Routings at the CFP4 Connector Area
CFP4 Connector Routing Topologies Design Example
Full CFP4 Channel Analysis Design Example (Excluding the Connector)
CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline
QSFP+ Module Assembly and Pinout
Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels
Recommended QSFP+ Signal Routing
QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline
SMA 2.4 mm Molex Connector Assembly
PCB Design Guidelines for Channels Using the 2.4 mm Connector
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector
Recommended PCB layout Design for Version-B SMA 2.4 mm Connector
Performance Comparison between Option1 and Option2 layout
Other 2.4 mm Connectors
2.4 mm Channel Specifications
2.4 mm Example Design Performance
Tyco/Amphenol Interlaken Connector Design Guideline
Connector Signal and Pin Assignment
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations
Interlaken Channel Interface Performance Example
Electrical Specifications
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm
Interlaken Interface Specification
Document Revision History for AN 766: Intel Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline

Back to home page