Embedded Peripherals IP User Guide - This user guide describes the embedded peripherals IP cores that work seamlessly with the Nios® V processor. - 2026-04-30

Version: 26.1

1. Introduction
1.1. Tool Support
1.2. Device Support
1.3. Driver Support
1.4. Embedded Peripherals IP User Guide Archives
1.5. Document Revision History for Embedded Peripherals IP User Guide
2. Avalon® -ST Serial Peripheral Interface Core
2.1. Functional Description
2.1.1. Interfaces
2.1.2. Operation
2.1.3. Timing
2.1.4. Limitations
2.2. Configuration
2.3. Avalon® -ST Serial Peripheral Interface Core Revision History
3. SPI Core
3.1. Core Overview
3.2. Functional Description
3.2.1. Example Configurations
3.2.2. Transmitter Logic
3.2.3. Receiver Logic
3.2.4. Host and Agent Modes
3.2.4.1. Host Mode Operation
3.2.4.2. Agent Mode Operation
3.2.4.3. Multi-Agent Environments
3.3. Configuration
3.3.1. Host/Agent Settings
3.3.1.1. Number of Select (SS_n) Signals
3.3.1.2. SPI Clock (sclk) Rate
3.3.1.3. Specify Delay
3.3.2. Data Register Settings
3.3.3. Timing Settings
3.3.4. Synchronizer Stages
3.4. Software Programming Model
3.4.1. Hardware Access Routines
3.4.1.1. alt_avalon_spi_command()
3.4.2. Software Files
3.4.3. Register Map
3.4.3.1. rxdata Register
3.4.3.2. txdata Register
3.4.3.3. status Register
3.4.3.4. control Register
3.4.3.5. slaveselect Register
3.4.3.6. end of packet value Register
3.5. Example Test Code
3.6. SPI Core Revision History
4. SPI Agent/JTAG to Avalon® Host Bridge Cores
4.1. Core Overview
4.2. Functional Description
4.3. Parameters
4.4. SPI Agent/JTAG to Avalon® Host Bridge Cores Revision History
5. Intel eSPI Agent Core
5.1. Functional Description
5.1.1. Link Layer
5.1.2. Transaction Layer
5.1.3. Channel Specific Layer
5.1.3.1. Peripheral Channel
5.1.3.2. Virtual Wire Channel
5.1.3.2.1. Interrupt Event
5.1.4. Port80 Implementation
5.1.5. VW message to Physical Port Implementation
5.1.6. Avalon® Memory-Mapped Interface Settings
5.2. Resource Utilization
5.3. IP Parameters
5.4. Interface Signals
5.5. Registers
5.5.1. Avalon® memory-mapped interface Accessible Registers
5.5.1.1. Status Register
5.5.1.2. Control Register
5.5.1.3. Error Register
5.5.2. eSPI Interface Accessible Registers
5.5.2.1. eSPI Status Register
5.5.2.2. Capabilities and Configuration Registers
5.6. Peripheral Channel Avalon Interface Use Model
5.7. Intel eSPI Agent Core Revision History
6. eSPI to LPC Bridge Core
6.1. Unsupported LPC Features
6.2. IP Parameters
6.3. Supported IP Clock Frequency
6.4. Functional Description
6.4.1. FIFO Implementation
6.4.2. Transaction Ordering Rule
6.4.3. eSPI Command to LPC Cycle Type Conversion
6.4.4. SERIRQ Interrupt Event
6.5. Interface Signals
6.6. Registers
6.6.1. Status Register
6.6.2. Error Register
6.7. eSPI to LPC Bridge Core Revision History
7. Ethernet MDIO Core
7.1. Core Overview
7.2. Functional Description
7.2.1. MDIO Frame Format (Clause 45)
7.2.2. MDIO Clock Generation
7.2.3. Interfaces
7.2.4. Operation
7.2.4.1. Write Operation
7.2.4.2. Read Operation
7.3. Parameter
7.4. Configuration Registers
7.5. Interface Signals
7.6. Ethernet MDIO Core Revision History
8. 16550 Compatible UART Core
8.1. Core Overview
8.2. Feature Description
8.2.1. Unsupported Features
8.2.2. Interface
8.2.3. General Architecture
8.2.4. 16550 UART General Programming Flow Chart
8.2.5. Configuration Parameters
8.2.6. DMA Support
8.2.7. FPGA Resource Usage
8.2.8. Timing and Fmax
8.2.9. Avalon® -MM Agent
8.2.9.1. Read behavior
8.2.9.2. Write behavior
8.2.10. Over-run/Under-run Conditions
8.2.10.1. Overrun
8.2.10.2. Receive Overrun Behavior
8.2.10.3. Transmit Overrun Behavior
8.2.10.4. Underrun
8.2.11. Hardware Auto Flow-Control
8.2.12. Clock and Baud Rate Selection
8.3. Software Programming Model
8.3.1. Overview
8.3.2. Supported Features
8.3.3. Unsupported Features
8.3.4. Configuration
8.3.5. 16550 UART API
8.3.5.1. Public APIs
8.3.5.2. Private APIs
8.3.5.3. UART Device Structure
8.3.6. Driver Examples
8.4. Address Map and Register Descriptions
8.4.1. rbr_thr_dll
8.4.2. ier_dlh
8.4.3. iir
8.4.4. fcr
8.4.5. lcr
8.4.6. mcr
8.4.7. lsr
8.4.8. msr
8.4.9. scr
8.4.10. afr
8.4.11. tx_low
8.5. 16550 Compatible UART Core Revision History
9. UART Core
9.1. Core Overview
9.2. Functional Description
9.2.1. Avalon® -MM Agent Interface and Registers
9.2.2. RS-232 Interface
9.2.3. Transmitter Logic
9.2.4. Receiver Logic
9.2.5. Baud Rate Generation
9.3. Instantiating the Core
9.3.1. Configuration Settings
9.3.1.1. Baud Rate Options
9.3.1.2. Baud Rate (bps) Setting
9.3.1.3. Baud Rate Can Be Changed By Software Setting
9.3.1.4. Data Bits, Stop Bits, Parity
9.3.1.5. Synchronizer Stages
9.3.1.6. Streaming Data (DMA) Control
9.3.1.6.1. Include End-of-Packet Register
9.3.2. Simulation Settings
9.3.2.1. Simulated Transmitter Baud Rate
9.3.2.2. Simulation Considerations
9.4. Software Programming Model
9.4.1. HAL System Library Support
9.4.1.1. Driver Options: Fast vs Small Implementations
9.4.1.1.1. UART API
9.4.1.1.2. UART Device Structure
9.4.1.2. ioctl() Operations
9.4.1.3. Limitations
9.4.2. Software Files
9.4.3. Register Map
9.4.3.1. rxdata Register
9.4.3.2. txdata Register
9.4.3.3. status Register
9.4.3.4. control Register
9.4.3.5. divisor Register (Optional)
9.4.3.6. endofpacket Register (Optional)
9.4.4. Interrupt Behavior
9.5. UART Core Revision History
10. Lightweight UART Core
10.1. Core Overview
10.2. Functional Description
10.2.1. Avalon® Memory-Mapped Agent Interface and Registers
10.2.2. RS-232 Interface
10.2.3. Transistor-Transistor Logic (TTL) Interface
10.2.4. Handshaking Signal (CTS/RTS Flow Control)
10.2.5. Transmitter Logic
10.2.6. Receiver Logic
10.2.7. Baud Rate Generation
10.3. Configuration Parameters
10.3.1. Implement TXFIFO and RXFIFO in Register
10.3.2. Depth of TXFIFO and RXFIFO
10.3.3. Remaining RXFIFO Depth to Assert Almost Full
10.3.4. Include CTS/RTS
10.4. Instantiating the Core
10.4.1. Baud Rate Options
10.4.2. Baud Rate (bps) Setting
10.4.3. Baud Rate Can Be Changed by Software Setting
10.4.4. Data Bits, Stop Bits, Parity
10.4.5. Synchronizer Stages
10.4.6. Streaming Data (DMA) Control
10.4.6.1. Include End-of-Packet Register
10.5. Software Programming Model
10.5.1. HAL System Library Support
10.5.1.1. Driver Options: Fast vs. Small Implementations
10.5.1.1.1. UART API
10.5.1.1.2. UART Device Structure
10.5.1.2. ioctl() Operations
10.5.2. Software Files
10.5.3. Supported Features
10.5.4. Register Map
10.5.4.1. Transmit Data FIFO (TXFIFO)
10.5.4.2. Receive data FIFO (RXFIFO)
10.5.4.3. Status Register
10.5.4.4. Control Register
10.5.4.5. Divisor Register
10.5.4.6. Endofpacket Register
10.5.4.7. RXFIFO Level Register (RXFIFO_LVL)
10.5.4.8. TXFIFO level register (TXFIFO_LVL)
10.5.5. Interrupt Behavior
10.6. Lightweight UART Core Revision History
11. JTAG UART Core
11.1. Core Overview
11.2. Functional Description
11.2.1. Avalon® Agent Interface and Registers
11.2.2. Read and Write FIFOs
11.2.3. JTAG Interface
11.2.4. Host-Target Connection
11.2.5. Operating System Code Page
11.3. Configuration
11.3.1. Configuration Page
11.3.1.1. Write FIFO Settings
11.3.1.2. Read FIFO Settings
11.4. Software Programming Model
11.4.1. HAL System Library Support
11.4.1.1. Driver Options: Fast vs. Small Implementations
11.4.1.2. ioctl() Operations
11.4.2. Software Files
11.4.3. Accessing the JTAG UART Core via a Host PC
11.4.4. Register Map
11.4.4.1. Data Register
11.4.4.2. Control Register
11.4.5. Interrupt Behavior
11.5. JTAG UART Core Revision History
12. Intel FPGA Avalon® Mailbox Core
12.1. Core Overview
12.2. Functional Description
12.2.1. Message Sending and Retrieval Process
12.2.2. Component Register Map
12.2.2.1. Command Register
12.2.2.2. Pointer Register
12.2.2.3. Status Register
12.2.2.4. Interrupt Masking Register
12.3. Interface
12.3.1. Component Interface
12.3.2. Component Parameterization
12.4. HAL Driver
12.4.1. Feature Description
12.4.1.1. Component Configuration
12.4.1.1.1. Interrupt Mode
12.4.1.1.2. Polling Mode
12.4.1.2. Driver Implementation
12.4.1.3. Driver Examples
12.5. Intel FPGA Avalon® Mailbox Core Revision History
13. Intel FPGA Avalon® Mutex Core
13.1. Core Overview
13.2. Functional Description
13.3. Configuration
13.4. Software Programming Model
13.4.1. Software Files
13.4.2. Hardware Access Routines
13.5. Mutex API
13.5.1. altera_avalon_mutex_is_mine()
13.5.2. altera_avalon_mutex_first_lock()
13.5.3. altera_avalon_mutex_lock()
13.5.4. altera_avalon_mutex_open()
13.5.5. altera_avalon_mutex_trylock()
13.5.6. altera_avalon_mutex_unlock()
13.6. Intel FPGA Avalon® Mutex Core Revision History
14. Intel FPGA Avalon® I2C (Host) Core
14.1. Core Overview
14.2. Feature Description
14.2.1. Supported Features
14.2.2. Unsupported Features
14.3. Configuration Parameters
14.4. Interface
14.5. Registers
14.5.1. Register Memory Map
14.5.2. Register Descriptions
14.5.2.1. Transfer Command FIFO (TFR_CMD)
14.5.2.2. Receive Data FIFO (RX_DATA)
14.5.2.3. Control Register (CTRL)
14.5.2.4. Interrupt Status Enable Register (ISER)
14.5.2.5. Interrupt Status Register (ISR)
14.5.2.6. Status Register (STATUS)
14.5.2.7. TFR CMD FIFO Level (TFR CMD FIFO LVL)
14.5.2.8. RX Data FIFO Level (RX Data FIFO LVL)
14.5.2.9. SCL Low Count (SCL LOW)
14.5.2.10. SCL High Count (SCL HIGH)
14.5.2.11. SDA Hold Count (SDA HOLD)
14.6. Reset and Clock Requirements
14.7. Functional Description
14.7.1. Overview
14.7.2. Configuring TFT_CMD Register Examples
14.7.2.1. 7-bit Addressing Mode
14.7.2.1.1. Host Transmitter Writes 2 Bytes to Agent Receiver
14.7.2.1.2. Host Receiver Reads 2 Bytes from Agent Transmitter
14.7.2.1.3. Combine Format (Host Writes 1 Byte and Changes Direction to Read 2 Bytes)
14.7.2.2. 10-bit Addressing Mode
14.7.2.2.1. Host Transmitter Writes 2 Bytes to Agent Receiver
14.7.2.2.2. Host Receiver Reads 2 Bytes from Agent Transmitter
14.7.3. I2C Serial Interface Connection
14.7.4. Avalon® -MM Agent Interface
14.7.5. Avalon® -ST Interface
14.7.6. Programming Model
14.8. Intel FPGA Avalon® I2C (Host) Core API
14.8.1. Optional Status Retrieval API
14.9. Intel FPGA Avalon® I2C (Host) Core Revision History
15. Altera I2C Slave to Avalon® -MM Master Bridge Core
15.1. Core Overview
15.2. Functional Description
15.2.1. Block Diagram
15.2.2. N-byte Addressing
15.2.3. N-byte Addressing with N-bit Address Stealing
15.2.4. Read Operation
15.2.4.1. Random Address Read
15.2.4.2. Sequential Address Read
15.2.4.3. Current Address Read
15.2.5. Write Operation
15.2.6. Interacting with Multi-Hosts
15.3. Platform Designer Parameters
15.4. Signals
15.5. How to Translate the Bridge's I2C Data and I2C I/O Ports to an I2C Interface
15.6. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core Revision History
16. I3C Controller
16.1. Core Overview
16.2. Feature Description
16.2.1. Supported Features
16.2.1.1. General Features
16.2.1.2. Secondary Controller Features
16.2.1.3. Target Features
16.2.2. Unsupported Features
16.3. IP Parameters
16.4. IP Ports and Interfaces
16.4.1. Clock and Reset
16.4.2. APB Interface
16.4.3. I3C Interface
16.4.4. Interrupt
16.5. Controller Role (Active Controller Mode)
16.5.1. Controller Role Overview
16.5.2. Controller Mode Data Structures
16.5.2.1. Command Queue Data Structure
16.5.2.1.1. Transfer Command Data Structure
16.5.2.1.2. Transfer Argument Data Structure
16.5.2.1.3. Short Data Argument Data Structure
16.5.2.1.4. Address Assignment Command Data Structure
16.5.2.1.5. Command Sequences Requirement
16.5.2.2. Response Queue Data Structure
16.5.2.3. IBI Status and Queue Data Structure
16.5.2.4. Device Address Table (DAT)
16.5.2.4.1. DAT Data Structure
16.5.2.4.2. DAT Management
16.5.2.5. Device Characteristics Table (DCT)
16.5.2.5.1. DCT Data Structure
16.5.2.5.2. DCT Management
16.5.3. Controller Mode Operation and Transfer Types
16.5.3.1. Private Transfer
16.5.3.2. Broadcast CCC Write Transfer
16.5.3.3. Directed CCC Read/Write Transfer
16.5.3.4. Directed CCC Read/Write Transfer to Multiple Targets
16.5.3.5. Data Packing and Unpacking for Controller
16.5.3.5.1. Overview
16.5.3.5.2. Unpacking Transmission Data by the I3C Controller IP from Transmit FIFO
16.5.3.5.3. Packing Read Data by the I3C Controller IP into Receive FIFO
16.5.3.5.3.1. Packing Private Read Data
16.5.3.5.3.2. Packing Any Read Data
16.5.3.5.3.3. Packing of Received ENTDAA Data into the DCT
16.5.4. Dynamic Address Assignment (DAA)
16.5.4.1. DAA Overview
16.5.4.1.1. DAA Required Conditions
16.5.4.2. DAA Methods
16.5.4.2.1. ENTDAA Procedure
16.5.4.2.2. SETDASA Procedure (Format 1: Primary)
16.5.4.2.3. SETDASA Procedure (Format 2: Point-to-Point, Minimal Bus)
16.5.4.2.4. SETAASA Procedure
16.5.4.2.5. SETNEWDA Procedure
16.5.5. In-Band Interrupt (IBI) Detection and Handling
16.5.5.1. IBI Detection Conditions
16.5.5.2. IBI Handling Overview
16.5.5.3. Controller Request (MR)
16.5.5.4. Slave Interrupt Request (SIR)
16.5.5.5. IBI Queue Data Structure
16.5.6. SCL Generation and Timings Based on Bus Configuration
16.5.7. Error Detection and Recovery
16.5.7.1. Error Codes
16.5.7.2. Error Types and Recovery Method
16.5.7.2.1. Error Type M0
16.5.7.2.2. Error Type M1
16.5.8. Defining Byte Support
16.5.9. Disabling and Terminating Transfer
16.5.9.1. Disable Controller Role
16.5.9.2. Terminate Bus Transfers
16.6. Target Role
16.6.1. Target Role Overview
16.6.2. I3C vs I2C Mode Transition
16.6.3. Target Mode Data Structures in Non-HCI Mode
16.6.3.1. Command Queue Data Structure
16.6.3.2. Response Queue Data Structure
16.6.4. Target Mode Operation and Transfer Types
16.6.4.1. CCC Transfers
16.6.4.1.1. CCC Handling
16.6.4.1.1.1. CCCs Handled via Configuration Parameters
16.6.4.1.1.2. CCCs Handled via Internal Registers
16.6.4.1.1.3. CCCs Handled via Port Signals
16.6.4.1.1.4. CCCs Handled via Both Port and Register Signals
16.6.4.1.2. CCC Updated Notification and Interrupt Handling
16.6.4.2. Private Transfers
16.6.4.2.1. Private Receive (Controller Write)
16.6.4.2.2. Private Transmit (Controller Read)
16.6.5. Command Pipeline and Response Queue Interrupt Aggregation
16.6.6. Error Detection and Recovery
16.6.6.1. Error Types and Recovery Methods
16.6.6.2. Error Codes
16.6.7. Disabling and Terminating Transfer
16.6.7.1. Disable Target Role
16.7. Programming And Usage Flows
16.7.1. Controller Mode Programming Flow
16.7.1.1. Programming Flow to Prepare the I3C Controller IP to Switch to Controller Mode
16.7.2. Target Mode Programming Flow
16.7.2.1. Programming Flow for Generating Target Interrupt Request
16.7.2.1.1. Programming Flow for Generating Target Interrupt Request Without Data
16.7.2.1.2. Programming Flow for Generating Target Interrupt Request With Data
16.7.2.2. Programming Flow for Generating Controller Request
16.7.2.3. Programming Flow to Disable Hot-Join (HJ) Capability
16.7.2.4. Programming Flow to Prepare the I3C Controller IP to Switch to Controller Mode
16.8. Registers Descriptions
16.8.1. DEVICE_CTRL (Device Control Register)
16.8.2. DEVICE_ADDR (Device Address Register)
16.8.3. HW_CAPABILITY (Hardware Capability Register)
16.8.4. COMMAND_QUEUE_PORT (Command Queue Port Register)
16.8.5. RESPONSE_QUEUE_PORT (Response Queue Port Register)
16.8.6. XFER_DATA_PORT (Transfer Data Port Register)
16.8.7. IBI_QUEUE_PORT (Controller Mode In-Band interrupt Queue Port Register)
16.8.8. QUEUE_THLD_CTRL (Queue Threshold Control Register)
16.8.9. DATA_BUFFER_THLD_CTRL (Data Buffer Threshold Control Register)
16.8.10. IBI_QUEUE_CTRL (Controller Mode IBI Queue Control Register)
16.8.11. IBI_MR_REQ_REJECT (Controller Mode IBI MR Rejection Control Register)
16.8.12. IBI_SIR_REQ_REJECT (Controller Mode IBI SIR Rejection Control Register)
16.8.13. RESET_CTRL (Reset Control Register)
16.8.14. SLV_EVENT_STATUS (Target Mode Event Status Register)
16.8.15. INTR_STATUS (Interrupt Status Register)
16.8.16. INTR_STATUS_EN (Interrupt Status Enable Register)
16.8.17. INTR_SIGNAL_EN (Interrupt Signal Enable Register)
16.8.18. INTR_FORCE (Interrupt Force Enable Register)
16.8.19. QUEUE_STATUS_LEVEL (Queue Status Level Register)
16.8.20. DATA_BUFFER_STATUS_LEVEL (Data Buffer Status Level Register)
16.8.21. PRESENT_STATE (Present State Register)
16.8.22. CCC_DEVICE_STATUS (Target Mode Device Operating Status Register)
16.8.23. DEVICE_ADDR_TABLE_POINTER (Controller Mode Device Address Table Pointer)
16.8.24. DEVICE_CHAR_TABLE_POINTER (Controller Mode Device Characteristics Table Pointer)
16.8.25. VENDOR_SPECIFIC_REG_POINTER (Controller Mode Vendor Specific Pointer Register)
16.8.26. SLV_MIPI_ID_VALUE (Target Mode Manufacturer ID Register)
16.8.27. SLV_PID_VALUE (Target Mode Provisional ID Register)
16.8.28. SLV_CHAR_CTRL (Target Mode Characteristic Register)
16.8.29. SLV_MAX_LEN (Target Mode Max Write/Read Length Register)
16.8.30. MAX_READ_TURNAROUND (Maximum Supported IBI Payload Size)
16.8.31. MAX_DATA_SPEED (Target Mode Maximum Data Speed Register)
16.8.32. SLV_INTR_REQ (Target Mode Interrupt Request Register)
16.8.33. SLV_SIR_DATA (Target Interrupt Request Data Register)
16.8.34. SLV_IBI_RESP (Target IBI Response Register)
16.8.35. DEVICE_CTRL_EXTENDED (Device Control Extended Register)
16.8.36. SCL_I3C_OD_TIMING (SCL I3C Open Drain Timing Register)
16.8.37. SCL_I3C_PP_TIMING (SCL I3C Push-Pull Timing Register)
16.8.38. SCL_I2C_FM_TIMING (SCL I2C Fast Mode Timing Register)
16.8.39. SCL_I2C_FMP_TIMING (SCL I2C Fast Mode Plus Timing Register)
16.8.40. SCL_EXT_LCNT_TIMING (SCL Extended Low Count Timing Register)
16.8.41. SCL_EXT_TERMN_LCNT_TIMING (SCL Termination Bit Low Count Timing Register)
16.8.42. SDA_HOLD_SWITCH_DLY_TIMING (SDA Hold and Mode Switch Delay Timing Register)
16.8.43. BUS_FREE_AVAIL_TIMING (Bus Free Timing Register)
16.8.44. BUS_IDLE_TIMING (Bus Idle Timing Register)
16.8.45. I3C_VER_ID (Version ID Register)
16.8.46. I3C_VER_TYPE (Version Type Register)
16.8.47. QUEUE_SIZE_CAPABILITY (Queue Size Capability Register)
16.8.48. DEV_CHAR_TABLEx_LOC1 (Device Characteristic Table Location-1 of Device1 to Device 11)
16.8.49. SEC_DEV_CHAR_TABLEx (Secondary Controller Device Characteristic Table Location of Device1 to Device 11)
16.8.50. DEV_CHAR_TABLEx_LOC2 (Device Characteristic Table Location-2 of Device1 to Device 11)
16.8.51. DEV_CHAR_TABLEx_LOC3 (Device Characteristic Table Location-3 of Device1 to Device 11)
16.8.52. DEV_CHAR_TABLEx_LOC4 (Device Characteristic Table Location-4 of Device1 to Device 11)
16.8.53. DEV_ADDR_TABLE_LOCx (Device Address Table of Device1 to Device 11)
16.9. Driver
16.9.1. Common API
16.9.2. Controller Mode API
16.9.3. Target Mode API
16.10. I3C Controller Revision History
17. EPCS/EPCQA Serial Flash Controller Core
17.1. Core Overview
17.2. Functional Description
17.2.1. Avalon® -MM Agent Interface and Registers
17.3. Configuration
17.4. Interface Signals
17.5. Software Programming Model
17.5.1. HAL System Library Support
17.5.2. Software Files
17.6. Driver API
17.7. EPCS/EPCQA Serial Flash Controller Core Revision History
18. Serial Flash Controller Core
18.1. Parameters
18.1.1. Configuration Device Types
18.1.2. I/O Mode
18.1.3. Chip Selects
18.1.4. Interface Signals
18.2. Registers
18.2.1. Register Memory Map
18.2.2. Register Descriptions
18.2.2.1. FLASH_RD_STATUS
18.2.2.2. FLASH_RD_SID
18.2.2.3. FLASH_RD_RDID
18.2.2.4. FLASH_MEM_OP
18.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command
18.2.2.4.1.1. Sector Protect
18.2.2.4.1.2. Sector Erase
18.2.2.5. FLASH_ISR
18.2.2.6. FLASH_IMR
18.2.2.7. FLASH_CHIP_SELECT
18.3. Nios® II and Nios® V Tools Support
18.3.1. Booting Nios® II from Flash
18.3.1.1. Flash Memory Map and Setting Nios® II Reset Vector when Using a Boot Copier
18.3.1.2. Boot Copier File
18.3.1.3. When Nios® II SBT will Append a Boot Copier
18.3.1.4. Creating HEX Programming File
18.3.1.5. Programming the Flash
18.3.1.6. Custom Boot Copiers
18.3.1.7. Executing in Place
18.3.2. Nios® II and Nios® V HAL Drivers
18.4. Driver API
18.5. Serial Flash Controller Core Revision History
19. Serial Flash Controller II Core
18.1. Parameters
19.1.1. Configuration Device Types
18.1.2. I/O Mode
18.1.3. Chip Selects
19.1.4. Interface Signals
19.1.4.1. Initial State of QSPI Flash Data Lines
18.2. Registers
19.2.1. Register Memory Map
19.2.2. Register Descriptions
18.2.2.1. FLASH_RD_STATUS
18.2.2.3. FLASH_RD_RDID
19.2.2.3. FLASH_MEM_OP
19.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
19.2.2.3.1.1. Sector Protect
19.2.2.3.1.2. Sector Erase
18.2.2.7. FLASH_CHIP_SELECT
19.2.2.5. EPCQ_FLAG_STATUS
19.2.2.6. DEVICE_ID_DATA_x
18.3. Nios® II and Nios® V Tools Support
18.3.1. Booting Nios® II from Flash
18.3.1.1. Flash Memory Map and Setting Nios® II Reset Vector when Using a Boot Copier
18.3.1.2. Boot Copier File
18.3.1.3. When Nios® II SBT will Append a Boot Copier
18.3.1.4. Creating HEX Programming File
18.3.1.5. Programming the Flash
18.3.1.6. Custom Boot Copiers
18.3.1.7. Executing in Place
19.3.2. Nios® II and Nios® V HAL Drivers
19.4. Driver API
19.5. Serial Flash Controller II Core Revision History
20. Generic QUAD SPI Controller Core
20.1. Parameters
20.1.1. Configuration Device Types
20.1.2. I/O Mode
20.1.3. Chip Selects
20.1.4. Interface Signals
20.2. Registers
20.2.1. Register Memory Map
20.2.2. Register Descriptions
20.2.2.1. FLASH_RD_STATUS
20.2.2.2. FLASH_RD_SID
20.2.2.3. FLASH_RD_RDID
20.2.2.4. FLASH_MEM_OP
19.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
19.2.2.3.1.1. Sector Protect
19.2.2.3.1.2. Sector Erase
20.2.2.5. FLASH_ISR
20.2.2.6. FLASH_IMR
20.2.2.7. FLASH_CHIP_SELECT
20.3. Nios® II and Nios® V Tools Support
20.3.1. Nios® II and Nios® V HAL Drivers
20.4. Driver API
20.5. Generic QUAD SPI Controller Core Revision History
21. Generic QUAD SPI Controller II Core
21.1. Parameters
21.1.1. Disable Dedicated Active Serial Interface
21.1.2. Enable SPI Pins Interface
21.1.3. Enable Flash Simulation Model
21.1.4. Configuration Device Types
20.1.2. I/O Mode
20.1.3. Chip Selects
21.2. Interface Signals
21.2.1. Initial State of QSPI Flash Data Lines
20.2. Registers
21.3.1. Register Memory Map
20.2.2. Register Descriptions
20.2.2.1. FLASH_RD_STATUS
20.2.2.3. FLASH_RD_RDID
19.2.2.3. FLASH_MEM_OP
19.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
19.2.2.3.1.1. Sector Protect
19.2.2.3.1.2. Sector Erase
20.2.2.7. FLASH_CHIP_SELECT
19.2.2.5. EPCQ_FLAG_STATUS
19.2.2.6. DEVICE_ID_DATA_x
20.3. Nios® II and Nios® V Tools Support
21.4.1. Nios® II and Nios® V HAL Drivers
21.5. Driver API
21.6. Generic QUAD SPI Controller II Core Revision History
22. Interval Timer Core
22.1. Core Overview
22.2. Functional Description
22.2.1. Avalon® -MM Agent Interface
22.3. IP Parameters
22.3.1. Timeout Period
22.3.2. Counter Size
22.3.3. Configuring the Timer as a Watchdog Timer
22.4. Driver Implementation
22.4.1. Interrupt Behavior
22.5. Register Map
22.6. HAL APIs and Macros
22.7. Interval Timer Core Revision History
23. Intel FPGA Avalon FIFO Memory Core
23.1. Core Overview
23.2. Functional Description
23.2.1. Avalon® -MM Write Agent to Avalon® -MM Read Agent
23.2.2. Avalon® -ST Sink to Avalon® -ST Source
23.2.3. Avalon® -MM Write Agent to Avalon® -ST Source
23.2.4. Avalon® -ST Sink to Avalon® -MM Read Agent
23.2.5. Status Interface
23.2.6. Clocking Modes
23.3. Configuration
23.3.1. FIFO Settings
23.3.2. Interface Parameters
23.3.3. Interface Signals
23.4. Software Programming Model
23.4.1. HAL System Library Support
23.4.2. Software Files
23.5. Programming with the Intel FPGA Avalon FIFO Memory
23.5.1. Software Control
23.5.2. Software Example
23.6. Intel FPGA Avalon FIFO Memory API
23.6.1. altera_avalon_fifo_init()
23.6.2. altera_avalon_fifo_read_status()
23.6.3. altera_avalon_fifo_read_ienable()
23.6.4. altera_avalon_fifo_read_almostfull()
23.6.5. altera_avalon_fifo_read_almostempty()
23.6.6. altera_avalon_fifo_read_event()
23.6.7. altera_avalon_fifo_read_level()
23.6.8. altera_avalon_fifo_clear_event()
23.6.9. altera_avalon_fifo_write_ienable()
23.6.10. altera_avalon_fifo_write_almostfull()
23.6.11. altera_avalon_fifo_write_almostempty()
23.6.12. altera_avalon_write_fifo()
23.6.13. altera_avalon_write_other_info()
23.6.14. altera_avalon_fifo_read_fifo()
23.6.15. altera_avalon_fifo_read_other_info()
23.7. Intel FPGA Avalon FIFO Memory Core Revision History
24. On-Chip Memory (RAM and ROM) Intel FPGA IP
24.1. Core Overview
24.2. Component-Level Design for On-Chip Memory
24.2.1. Memory Type
24.2.2. Size
24.2.3. Read Latency
24.2.4. ROM/RAM Memory Protection
24.2.5. ECC Parameter
24.2.6. Memory Initialization
24.3. Platform Designer System-Level Design for On-Chip Memory
24.4. Simulation for On-Chip Memory
24.5. Quartus® Prime Project-Level Design for On-Chip Memory
24.6. Board-Level Design for On-Chip Memory
24.7. Example Design with On-Chip Memory
24.8. On-Chip Memory (RAM and ROM) Intel FPGA IP Revision History
25. On-Chip Memory II (RAM or ROM) Intel FPGA IP
25.1. Core Overview
25.2. Embedded Memory Architecture and Features
25.3. Component-Level Configurations
25.3.1. Avalon Memory-Mapped On-Chip Memory II Configuration
25.3.1.1. Avalon Memory-Mapped Interface
25.3.1.2. Memory Type
25.3.1.3. Clock Enable
25.3.1.4. Size
25.3.1.5. Read During Write Mode
25.3.1.6. Read Latency
25.3.1.7. ROM/RAM Memory Protection
25.3.1.8. ECC
25.3.1.9. Memory Initialization
25.3.2. AXI-4 On-Chip Memory II Configuration
25.3.2.1. AXI-4 Interface
25.3.2.2. Memory Type
25.3.2.3. Clock Enable
25.3.2.4. Size
25.3.2.5. Read During Write Mode
25.3.2.6. ROM/RAM Memory Protection
25.3.2.7. Memory Initialization
25.3.2.8. ECC
25.3.2.8.1. Supported ECC Configuration
25.3.2.8.2. Supported ECC Features
25.3.2.8.3. ECC Status Reporting
25.3.2.8.4. ECC Encoder Bypass
25.3.2.8.5. Read Modify Write
25.4. Interface Signals
25.4.1. Avalon Memory-Mapped Interface Signals
25.4.2. Avalon Memory-Mapped Interface Timing Diagram
25.4.3. AXI-4 Lite Interface Signals
25.4.4. AXI-4 Interface Signals
25.4.5. AXI Interface Timing Diagram
25.5. Control and Status Registers
25.5.1. Register Memory Map
25.5.2. Register Descriptions
25.6. Software Programming Model
25.6.1. Read ECC Error Status FIFO
25.6.2. Enable Encoder Bypass Feature
25.7. Platform Designer System-Level Design for On-Chip Memory II
25.8. Simulation for On-Chip Memory II
25.9. Quartus® Prime Project-Level Design for On-Chip Memory II
25.10. Board-Level Design for On-Chip Memory II
25.11. Example Design with On-Chip Memory II
25.12. On-Chip Memory II (RAM and ROM) Intel FPGA IP Revision History
26. PIO Core
26.1. Core Overview
26.2. Functional Description
26.2.1. Data Input and Output
26.2.2. Edge Capture
26.2.3. IRQ Generation
26.3. Example Configurations
26.3.1. Avalon® -MM Interface
26.4. Configuration
26.4.1. Basic Settings
26.4.1.1. Width
26.4.1.2. Direction
26.4.1.3. Output Port Reset Value
26.4.1.4. Output Register
26.4.2. Input Options
26.4.2.1. Edge Capture Register
26.4.2.2. Interrupt
26.4.3. Simulation
26.5. Software Programming Model
26.5.1. Software Files
26.5.2. Register Map
26.5.2.1. data Register
26.5.2.2. direction Register
26.5.2.3. interruptmask Register
26.5.2.4. edgecapture Register
26.5.2.5. outset and outclear Register
26.5.3. Interrupt Behavior
26.5.4. Software Files
26.6. PIO Core Revision History
27. PLL Cores
27.1. Core Overview
27.2. Functional Description
27.2.1. ALTPLL IP Core
27.2.2. Clock Outputs
27.2.3. PLL Status and Control Signals
27.2.4. System Reset Considerations
27.3. Instantiating the Avalon® ALTPLL Core
27.4. Instantiating the PLL Core
27.5. Hardware Simulation Considerations
27.6. Register Definitions and Bit List
27.6.1. Status Register
27.6.2. Control Register
27.6.3. Phase Reconfig Control Register
27.7. PLL Cores Revision History
28. DMA Controller Core
28.1. Core Overview
28.2. Functional Description
28.2.1. Setting Up DMA Transactions
28.2.2. The Host Read and Write Ports
28.2.3. Addressing and Address Incrementing
28.3. Parameters
28.3.1. DMA Parameters (Basic)
28.3.2. Advanced Options
28.4. Software Programming Model
28.4.1. HAL System Library Support
28.4.2. Software Files
28.4.3. Register Map
28.4.4. Interrupt Behavior
28.5. DMA Controller Core Revision History
29. Modular Scatter-Gather DMA Core
29.1. Core Overview
29.2. Feature Description
29.2.1. mSGDMA IP with Prefetcher Disabled
29.2.2. mSGDMA IP with Prefetcher Enabled
29.3. mSGDMA Descriptors
29.3.1. Read and Write Address Fields
29.3.2. Length Field
29.3.3. Sequence Number Field
29.3.4. Read and Write Burst Count Fields
29.3.5. Read and Write Stride Fields
29.3.6. Control Field
29.4. mSGDMA Descriptors with Prefetcher
29.4.1. Descriptor Format
29.4.2. Responder Descriptor Format
29.4.3. Descriptor Fields Definition
29.4.4. Descriptor Processing with Prefetcher Enabled
29.5. mSGDMA IP Interface
29.5.1. Control and Status Register Agent Interface
29.5.2. Source and Destination Data Path Interface
29.5.3. Prefetcher Disabled Mode Interface
29.5.4. Prefetcher Enabled Mode Interface
29.5.5. IP Interface Signals
29.6. mSGDMA Interrupt
29.7. Register Map of mSGDMA
29.7.1. Status Register (Offset 0x0)
29.7.2. Control Register (Offset 0x4)
29.7.3. Read and Write Fill Level Register (Offset 0x8)
29.7.4. Response Fill Level Register (Offset 0xC)
29.7.5. Sequence Number Register (Offset 0x10)
29.7.6. Component Configuration 1 Register (Offset 0x14)
29.7.7. Component Configuration 2 Register (Offset 0x18)
29.7.8. Component Specification Register (Offset 0x1C)
29.7.9. Response Register (when MM response port is enabled)
29.7.10. Prefetcher Register
29.8. Parameters
29.8.1. mSGDMA Parameter Editor
29.9. mSGDMA Programming Model
29.9.1. Stop DMA Operation
29.9.2. Stop Descriptor Operation
29.9.3. Recovery from Stopped on Error and Stopped on Early Termination
29.10. mSGDMA Prefetcher Programming Model
29.10.1. Setting up Descriptor and mSGDMA Configuration Flow
29.10.2. Resetting Prefetcher Core Flow
29.11. Driver Implementation
29.11.1. alt_msgdma_standard_descriptor_async_transfer
29.11.2. alt_msgdma_extended_descriptor_async_transfer
29.11.3. alt_msgdma_standard_descriptor_sync_transfer
29.11.4. alt_msgdma_extended_descriptor_sync_transfer
29.11.5. alt_msgdma_descriptor_sync_transfer
29.11.6. alt_msgdma_construct_standard_st_to_mm_descriptor
29.11.7. alt_msgdma_construct_standard_mm_to_st_descriptor
29.11.8. alt_msgdma_construct_standard_mm_to_mm_descriptor
29.11.9. alt_msgdma_construct_extended_st_to_mm_descriptor
29.11.10. alt_msgdma_construct_extended_mm_to_st_descriptor
29.11.11. alt_msgdma_construct_extended_mm_to_mm_descriptor
29.11.12. alt_msgdma_construct_prefetcher_standard_mm_to_mm_descriptor
29.11.13. alt_msgdma_construct_prefetcher_standard_st_to_mm_descriptor
29.11.14. alt_msgdma_construct_prefetcher_standard_mm_to_st_descriptor
29.11.15. alt_msgdma_construct_prefetcher_extended_mm_to_mm_descriptor
29.11.16. alt_msgdma_construct_prefetcher_extended_st_to_mm_descriptor
29.11.17. alt_msgdma_construct_prefetcher_extended_mm_to_st_descriptor
29.11.18. alt_msgdma_prefetcher_add_standard_desc_to_list
29.11.19. alt_msgdma_prefetcher_add_extended_desc_to_list
29.11.20. alt_msgdma_start_prefetcher_with_std_desc_list
29.11.21. alt_msgdma_start_prefetcher_with_extd_desc_list
29.11.22. alt_msgdma_register_callback
29.11.23. alt_msgdma_open
29.11.24. alt_msgdma_init
29.12. Example Code Using mSGDMA Core
29.13. Modular Scatter-Gather DMA Prefetcher Core
29.13.1. Functional Description
29.13.1.1. Supported Features
29.13.1.2. Architecture Overview
29.13.2. Descriptor Format
29.13.2.1. Descriptor Fields Definition
29.13.2.1.1. Next Descriptor Pointer
29.13.2.1.2. Actual Bytes Transferred
29.13.2.2. Descriptor Processing
29.13.3. Registers
29.13.3.1. Register Map
29.13.3.2. Control Register
29.13.3.3. Descriptor Polling Frequency
29.13.3.4. Status
29.13.4. Interfaces
29.13.4.1. Avalon® -MM Read Descriptor
29.13.4.2. Avalon® -MM Write Descriptor
29.13.4.3. Avalon® -MM CSR
29.13.4.4. Avalon® -ST Descriptor Source
29.13.4.5. Avalon® -ST Response
29.13.4.6. IRQ Interface
29.13.5. Software Programming Model
29.13.5.1. Setting up Descriptor and mSGDMA Configuration Flow
29.13.5.2. Resetting Prefetcher Core Flow
29.13.6. Parameters
29.14. Modular Scatter-Gather DMA Dispatcher Core
29.14.1. Block Diagram
29.14.2. Functional Description
29.14.3. mSGDMA Descriptors
29.14.3.1. Descriptor Format
29.14.3.2. Descriptor Fields Definition
29.14.4. Interfaces
29.14.4.1. IP Interface
29.14.4.1.1. Control and Status Register Agent Interface (CSR)
29.14.4.1.2. Descriptor Interface
29.14.4.1.3. Response Interface
29.14.4.2. Resets
29.14.4.3. Clocks
29.14.5. Interrupts
29.14.6. mSGDMA Programming Model
29.9.1. Stop DMA Operation
29.9.2. Stop Descriptor Operation
29.9.3. Recovery from Stopped on Error and Stopped on Early Termination
29.14.7. Register Descriptions
29.14.7.1. Register Map of mSGDMA Dispatcher IP
29.7.1. Status Register (Offset 0x0)
29.7.2. Control Register (Offset 0x4)
29.7.3. Read and Write Fill Level Register (Offset 0x8)
29.7.4. Response Fill Level Register (Offset 0xC)
29.7.5. Sequence Number Register (Offset 0x10)
29.7.6. Component Configuration 1 Register (Offset 0x14)
29.7.7. Component Configuration 2 Register (Offset 0x18)
29.7.8. Component Specification Register (Offset 0x1C)
29.7.9. Response Register (when MM response port is enabled)
29.15. Modular Scatter-Gather DMA Write Master Core
29.15.1. Block Diagram
29.15.2. Functional Description
29.15.2.1. Command Fields Definition
29.15.2.2. Response Fields Definition
29.15.3. Interfaces
29.15.3.1. Data Write Master Interface (data_write_master)
29.15.3.2. Data Sink Interface (data_sink)
29.15.3.3. Write Command Sink Interface (command_sink)
29.15.3.4. Write Response Source Interface (response_source)
29.15.4. Parameters
29.16. Modular Scatter-Gather DMA Read Master Core
29.16.1. Block Diagram
29.16.2. Functional Description
29.16.2.1. Command Fields Definition
29.16.2.2. Response Fields Definition
29.15.3. Interfaces
29.16.3.1. Data Read Master Interface (data_read_master)
29.16.3.2. Data Source Interface (data_source)
29.16.3.3. Read Command Sink Interface (command_sink)
29.16.3.4. Read Response Source Interface (response_source)
29.16.4. Parameters
29.17. Modular Scatter-Gather DMA Core Revision History
30. Scatter-Gather DMA Controller Core
30.1. Core Overview
30.1.1. Example Systems
30.1.2. Comparison of SG-DMA Controller Core and DMA Controller Core
30.2. Resource Usage and Performance
30.3. Functional Description
30.3.1. Functional Blocks and Configurations
30.3.2. DMA Descriptors
30.3.3. Error Conditions
30.4. Parameters
30.5. Simulation Considerations
30.6. Software Programming Model
30.6.1. HAL System Library Support
30.6.2. Software Files
30.6.3. Register Maps
30.6.4. DMA Descriptors
30.6.5. Timeouts
30.7. Programming with SG-DMA Controller
30.7.1. Data Structure
30.7.2. SG-DMA API
30.7.3. alt_avalon_sgdma_do_async_transfer()
30.7.4. alt_avalon_sgdma_do_sync_transfer()
30.7.5. alt_avalon_sgdma_construct_mem_to_mem_desc()
30.7.6. alt_avalon_sgdma_construct_stream_to_mem_desc()
30.7.7. alt_avalon_sgdma_construct_mem_to_stream_desc()
30.7.8. alt_avalon_sgdma_enable_desc_poll()
30.7.9. alt_avalon_sgdma_disable_desc_poll()
30.7.10. alt_avalon_sgdma_check_descriptor_status()
30.7.11. alt_avalon_sgdma_register_callback()
30.7.12. alt_avalon_sgdma_start()
30.7.13. alt_avalon_sgdma_stop()
30.7.14. alt_avalon_sgdma_open()
30.8. Scatter-Gather DMA Controller Core Revision History
31. Video Sync Generator and Pixel Converter Cores
31.1. Core Overview
31.2. Video Sync Generator
31.2.1. Functional Description
31.2.2. Parameters
31.2.3. Signals
31.2.4. Timing Diagrams
31.3. Pixel Converter
31.3.1. Functional Description
31.3.2. Parameters
31.3.3. Signals
31.4. Hardware Simulation Considerations
31.5. Video Sync Generator and Pixel Converter Cores Revision History
32. Intel FPGA Interrupt Latency Counter Core
32.1. Core Overview
32.2. Feature Description
32.2.1. Avalon® -MM Compliant CSR Registers
32.2.1.1. Control Register
32.2.1.2. Frequency Register
32.2.1.3. Counter Stop Registers
32.2.1.4. Latency Data Registers
32.2.1.5. Data Valid Registers
32.2.1.6. IRQ Active Registers
32.2.2. 32-bit Counter
32.2.3. Interrupt Detector
32.3. Component Interface
32.4. Component Parameterization
32.5. Software Access
32.5.1. Routine for Level Sensitive Interrupts
32.5.2. Routine for Edge/Pulse Sensitive Interrupts
32.6. Implementation Details
32.6.1. Interrupt Latency Counter Architecture
32.7. IP Caveats
32.8. Intel FPGA Interrupt Latency Counter Core Revision History
33. Performance Counter Unit Core
33.1. Core Overview
33.2. Functional Description
33.2.1. Section Counters
33.2.2. Global Counter
33.2.3. Register Map
33.2.4. System Reset
33.3. Configuration
33.3.1. Define Counters
33.3.2. Multiple Clock Domain Considerations
33.4. Hardware Simulation Considerations
33.5. Software Programming Model
33.5.1. Software Files
33.5.2. Using the Performance Counter
33.5.3. Interrupt Behavior
33.6. Performance Counter API
33.6.1. PERF_RESET()
33.6.2. PERF_START_MEASURING()
33.6.3. PERF_STOP_MEASURING()
33.6.4. PERF_BEGIN()
33.6.5. PERF_END()
33.6.6. perf_print_formatted_report()
33.6.7. perf_get_total_time()
33.6.8. perf_get_section_time()
33.6.9. perf_get_num_starts()
33.6.10. alt_get_cpu_freq()
33.7. Performance Counter Core Revision History
34. Vectored Interrupt Controller Core
34.1. Core Overview
34.2. Functional Description
34.2.1. External Interfaces
34.2.1.1. clk
34.2.1.2. irq_input
34.2.1.3. interrupt_controller_out
34.2.1.4. interrupt_controller_in
34.2.1.5. csr_access
34.2.2. Functional Blocks
34.2.2.1. Interrupt Request Block
34.2.2.2. Priority Processing Block
34.2.2.3. Vector Generation Block
34.2.3. Daisy Chaining VIC Cores
34.2.4. Latency Information
34.3. Register Maps
34.4. Parameters
34.5. Intel FPGA HAL Software Programming Model
34.5.1. Software Files
34.5.2. Macros
34.5.3. Data Structure
34.5.4. VIC API
34.5.4.1. alt_vic_sw_interrupt_set()
34.5.4.2. alt_vic_sw_interrupt_clear()
34.5.4.3. alt_vic_sw_interrupt_status()
34.5.4.4. alt_vic_irq_set_level()
34.5.5. Run-time Initialization
34.5.6. Board Support Package
34.5.6.1. altera_vic_driver.enable_preemption
34.5.6.2. altera_vic_driver.enable_preemption_into_new_register_set
34.5.6.3. altera_vic_driver.enable_preemption_rs_<n>
34.5.6.4. altera_vic_driver.linker_section
34.5.6.5. altera_vic_driver.<name>.vec_size
34.5.6.6. altera_vic_driver.<name>.irq<n>_rrs
34.5.6.7. altera_vic_driver.<name>.irq<n>_ril
34.5.6.8. altera_vic_driver.<name>.irq<n>_rnmi
34.5.6.9. Default Settings for RRS and RIL
34.5.6.10. VIC BSP Design Rules for Intel FPGA HAL Implementation
34.5.6.11. RTOS Considerations
34.6. Implementing the VIC in Platform Designer
34.6.1. Adding VIC Hardware
34.6.1.1. Adding the EIC Interface Shadow Register Set
34.6.1.2. VIC Instantiation, Parameterization, and Connection
34.6.1.2.1. Instantiation
34.6.1.2.2. Parameterization
34.6.1.2.3. VIC Connections
34.6.2. Software for VIC
34.6.2.1. alt_ic_isr_register() versus alt_irq_register()
34.7. Example Designs
34.7.1. Example Description
34.7.2. Example Usage
34.7.3. Software Description
34.7.4. Positioning the ISR in Vector Table
34.7.4.1. Increase the Vector Table Entry Size
34.7.4.2. Do Not Register the ISR
34.7.4.3. Insert ISR in Vector Table
34.7.5. Latency Measurement with the Performance Counter
34.8. Advanced Topics
34.8.1. Real Time Latency Concerns
34.8.1.1. Pipeline Latency
34.8.1.2. Cause Latency
34.8.1.3. Selection Latency
34.8.1.4. Funnel Latency
34.8.1.5. Compiler-Related Latency
34.8.2. Software Interrupt
34.9. Vectored Interrupt Controller Core Revision History
35. System ID Peripheral Core
35.1. Core Overview
35.2. Functional Description
35.3. Configuration in Quartus® Prime Pro Edition
35.3.1. System ID
35.3.2. System Generation Timestamp
35.4. Configuration in Quartus® Prime Standard Edition
35.4.1. System ID
35.4.2. System Generation Timestamp
35.5. Software Programming Model
35.5.1. alt_avalon_sysid_qsys_test()
35.6. System ID Core Revision History
36. Intel FPGA GMII to RGMII Converter Core
36.1. Core Overview
36.2. Feature Description
36.2.1. Supported Features
36.2.2. Unsupported Features
36.3. Parameters
36.3.1. IP Configuration Parameter
36.4. Intel FPGA GMII to RGMII Converter Core Interface
36.5. Functional Description
36.5.1. Architecture
36.5.1.1. Data Path
36.5.1.2. Clock Scheme
36.5.1.2.1. Transmit
36.5.1.2.2. Receive
36.6. Intel FPGA HPS EMAC Interface Splitter Core
36.6.1. Parameter
36.6.1.1. System Info Parameter
36.6.1.2. HDL Parameter
36.6.1.3. Interface Signals
36.6.1.4. Register
36.6.1.4.1. Register Memory Map
36.6.1.4.2. Register Description
36.6.1.4.2.1. Control Register
36.6.1.5. Avalon® -MM Agent Interface
36.7. Intel FPGA GMII to RGMII Converter Core Revision History
37. HPS GMII to RGMII Adapter IP
37.1. Core Overview
37.2. Feature Description
37.2.1. Supported Features
37.2.2. Unsupported Features
37.3. Parameters
37.3.1. IP Configuration Parameter
37.4. HPS GMII to RGMII Adapter IP Interface
37.5. Functional Description
37.5.1. Architecture
37.5.1.1. Data Path
37.5.1.2. Clock Scheme
37.5.1.2.1. Transmit
37.5.1.2.2. Receive
37.6. HPS GMII to RGMII Adapter IP Revision History
38. Intel FPGA MII to RMII Converter Core
38.1. Supported Features
38.2. Interface Signals
38.3. Parameters
38.4. Functional Description
38.4.1. Clocking Scheme
38.4.2. Transmit Interface
38.4.3. Receive Interface
38.5. Intel FPGA MII to RMII Converter Core Revision History
39. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core IP
39.1. Core Overview
39.2. Feature Description
39.2.1. Supported Features
39.3. Core Architecture
39.3.1. Data Path
39.3.2. Clock Scheme
39.3.3. MAC Speed
39.3.4. Transmit Elastic Buffer
39.3.4.1. GMII to MII Mode Transition
39.3.5. Avalon® Memory-Mapped Interface Agent Interface
39.3.6. Programming Model
39.4. Configuration Parameters
39.5. Interface
39.6. Registers
39.6.1. Register Memory Map
39.6.2. Register Description
39.7. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge IP Core Revision History
40. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core
40.1. Supported Features
40.2. Functional Description
40.3. Interface Signals
40.4. Register Memory Map and Description
40.5. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core Revision History
41. Intel FPGA MSI to GIC Generator Core
41.1. Core Overview
41.2. Background
41.3. Feature Description
41.3.1. Interrupt Servicing Process
41.3.2. Registers of Component
41.3.2.1. Status Register
41.3.2.2. Error Register
41.3.2.3. Interrupt Mask Register
41.3.3. Unsupported Feature
41.4. Intel FPGA MSI to GIC Generator Core Revision History
42. Cache Coherency Translator IP
42.1. Core Overview
42.2. IP Parameters
42.3. Use Case
42.4. Functional Description
42.4.1. Fixed Value
42.4.2. GPIO Mode
42.4.3. CSR Mode
42.5. Interface Signals
42.6. Clocking
42.7. Reset
42.8. Clock and Reset Signals
42.9. Register Description
42.10. Cache Coherency Translator IP Revision History
43. Altera ACE5-Lite Cache Coherency Translator
43.1. Core Overview
43.2. IP Parameters
43.3. Use Case
43.4. Functional Description
43.5. Interface Signals
43.6. Clocking
43.7. Reset
43.8. Clock and Reset Signals
43.9. Register Description
43.10. Altera ACE5-Lite Cache Coherency Translator Revision History

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