MAX 10 FPGA Device Architecture - Provides device architecture information for the Intel MAX 10 FPGA. - 2022-10-31

1. Intel MAX 10 FPGA Device Architecture
1.1. Logic Array Block
1.1.1. LAB Interconnects
1.1.2. LAB Control Signals
1.1.3. Logic Elements
1.1.3.1. LE Features
1.1.3.2. LE Operating Modes
1.1.3.2.1. Normal Mode
1.1.3.2.2. Arithmetic Mode
1.2. Embedded Memory
1.3. Embedded Multiplier
1.3.1. 18-Bit Multipliers
1.3.2. 9-Bit Multipliers
1.4. Clocking and PLL
1.4.1. Global Clock Networks
1.4.2. Internal Oscillator
1.4.3. PLL Block and Locations
1.5. General Purpose I/O
1.5.1. Intel MAX 10 I/O Banks Architecture
1.5.2. Intel MAX 10 I/O Banks Locations
1.6. High-Speed LVDS I/O
1.6.1. Intel MAX 10 High-Speed LVDS Circuitry
1.6.2. Intel MAX 10 High-Speed LVDS I/O Location
1.7. External Memory Interface
1.7.1. Intel MAX 10 I/O Banks for External Memory Interface
1.8. Analog to Digital Converter
1.8.1. ADC Block Locations
1.9. Configuration Schemes
1.9.1. JTAG Configuration
1.9.2. Internal Configuration
1.10. User Flash Memory
1.11. Power Management
1.11.1. Single-Supply Device
1.11.2. Dual-Supply Device
1.11.3. Power Management Controller Scheme
1.11.4. Hot Socketing
1.12. Document Revision History for Intel MAX 10 FPGA Device Architecture

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