AN 775: Generating Initial I/O Timing Data and I/O Element Delays for Altera FPGAs - Describes generation of initial I/O timing data and I/O element delay information for Altera FPGA devices using the Quartus Prime software GUI or Tcl commands. Initial I/O timing data is useful for early pin planning and PCB design. - 2025-09-29

Version

25.3

Product Type

Device Families > Agilex Families > Agilex 7 > M-Series

Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition

Device Families > Arria Families > Arria 10

Device Families > Agilex Families

Device Families > Agilex Families > Agilex 7 > F-Series

Device Families > Stratix Families > Stratix 10

Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software

Device Families > Agilex Families > Agilex 7

Device Families > Arria Families

Device Families > Stratix Families

Device Families > Agilex Families > Agilex 7 > I-Series

Resource Type

Documentation > Application Notes

Source Name

DITA