Stratix V Avalon-ST Interface for PCIe Solutions User Guide - Hard IP for PCI Express Endpoint and Root Port, Gen1, Gen2, Gen3 - 2019-05-03

Version: 15.1

1. Datasheet
1.1. Stratix V Avalon-ST Interface for PCIe Datasheet
1.1.1. Features
1.2. Release Information
1.3. Device Family Support
1.4. Configurations
1.5. Avalon-ST Example Designs
1.6. Debug Features
1.7. IP Core Verification
1.7.1. Compatibility Testing Environment
1.8. Resource Utilization
1.9. Recommended Speed Grades
1.10. Creating a Design for PCI Express
2. Getting Started with the Stratix V Hard IP for PCI Express
2.1. Qsys Design Flow
2.1.1. Generating the Testbench
2.1.2. Simulating the Example Design
2.1.3. Generating Synthesis Files
2.1.4. Understanding the Files Generated
2.1.5. Understanding Simulation Log File Generation
2.1.6. Understanding Physical Placement of the PCIe IP Core
2.1.7. Compiling the Design in the Qsys Design Flow
2.1.8. Modifying the Example Design
2.1.9. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
3.1. Copying the Configuration Space Bypass Mode Example Design
3.2. Generating the Qsys System
2.1.3. Generating Synthesis Files
3.2.2. Understanding the Generated Files
2.1.5. Understanding Simulation Log File Generation
3.3. Simulating the Example Design
3.3.1. Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface
3.3.2. Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface
3.3.3. Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface
3.3.4. Partial Transcript for Configuration Space Bypass Simulation
4. Parameter Settings
4.1. System Settings
4.2. Base Address Register (BAR) and Expansion ROM Settings
4.3. Base and Limit Registers for Root Ports
4.4. Device Identification Registers
4.5. PCI Express and PCI Capabilities Parameters
4.5.1. PCI Express and PCI Capabilities
4.5.2. Error Reporting
4.5.3. Link Capabilities
4.5.4. MSI and MSI-X Capabilities
4.5.5. Slot Capabilities
4.5.6. Power Management
4.6. Vendor Specific Extended Capability (VSEC)
4.7. PHY Characteristics
5. Interfaces and Signal Descriptions
5.1. Avalon‑ST RX Interface
5.1.1. Avalon-ST RX Component Specific Signals
5.1.2. Data Alignment and Timing for the 64‑Bit Avalon -ST RX Interface
5.1.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
5.1.3.1. Single Packet Per Cycle
5.1.4. Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface
5.1.5. Tradeoffs to Consider when Enabling Multiple Packets per Cycle
5.2. Avalon-ST TX Interface
5.2.1. Avalon-ST Packets to PCI Express TLPs
5.2.2. Data Alignment and Timing for the 64‑Bit Avalon-ST TX Interface
5.2.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface
5.2.4. Data Alignment and Timing for the 256‑Bit Avalon‑ST TX Interface
5.2.4.1. Single Packet Per Cycle
5.2.4.2. Multiple Packets per Cycle on the Avalon-ST TX 256-Bit Interface
5.2.5. Root Port Mode Configuration Requests
5.3. Clock Signals
5.4. Reset, Status, and Link Training Signals
5.5. ECRC Forwarding
5.6. Error Signals
5.7. Interrupts for Endpoints
5.8. Interrupts for Root Ports
5.9. Completion Side Band Signals
5.10. Configuration Space Bypass Mode Interface Signals
5.11. Parity Signals
5.12. LMI Signals
5.13. Transaction Layer Configuration Space Signals
5.13.1. Configuration Space Register Access Timing
5.13.2. Configuration Space Register Access
5.14. Hard IP Reconfiguration Interface
5.15. Power Management Signals
5.16. Physical Layer Interface Signals
5.16.1. Transceiver Reconfiguration
5.16.2. Serial Data Signals
5.16.2.1. Physical Layout of Hard IP in Stratix V GX/GT/GS Devices
5.16.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5.16.3. PIPE Interface Signals
5.16.4. Test Signals
6. Registers
6.1. Correspondence between Configuration Space Registers and the PCIe Specification
6.2. Type 0 Configuration Space Registers
6.3. Type 1 Configuration Space Registers
6.4. PCI Express Capability Structures
6.5. Intel-Defined VSEC Registers
6.6. CvP Registers
6.7. Uncorrectable Internal Error Mask Register
6.8. Uncorrectable Internal Error Status Register
6.9. Correctable Internal Error Mask Register
6.10. Correctable Internal Error Status Register
7. Reset and Clocks
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
7.2. Clocks
7.2.1. Clock Domains
7.2.1.1. pclk
7.2.1.2. coreclkout_hip
7.2.1.3. pld_clk
7.2.2. Clock Summary
8. Interrupts
8.1. Interrupts for Endpoints
8.1.1. MSI and Legacy Interrupts
8.1.2. MSI-X
8.1.3. Implementing MSI-X Interrupts
8.1.4. Legacy Interrupts
8.2. Interrupts for Root Ports
9. Error Handling
9.1. Physical Layer Errors
9.2. Data Link Layer Errors
9.3. Transaction Layer Errors
9.4. Error Reporting and Data Poisoning
9.5. Uncorrectable and Correctable Error Status Bits
10. PCI Express Protocol Stack
10.1. Top-Level Interfaces
10.1.1. Avalon-ST Interface
10.1.2. Clocks and Reset
10.1.3. Local Management Interface (LMI Interface)
10.1.4. Hard IP Reconfiguration
10.1.5. Transceiver Reconfiguration
10.1.6. Interrupts
10.1.7. PIPE
10.2. Transaction Layer
10.2.1. Configuration Space
10.2.2. Configuration Space Bypass Mode
Error Checking and Handling in Configuration Space Bypass Mode
Protocol Extensions Supported
10.3. Data Link Layer
10.4. Physical Layer
11. Transaction Layer Protocol (TLP) Details
11.1. Supported Message Types
11.1.1. INTX Messages
11.1.2. Power Management Messages
11.1.3. Error Signaling Messages
11.1.4. Locked Transaction Message
11.1.5. Slot Power Limit Message
11.1.6. Vendor-Defined Messages
11.1.7. Hot Plug Messages
11.2. Transaction Layer Routing Rules
11.3. Receive Buffer Reordering
11.3.1. Using Relaxed Ordering
12. Throughput Optimization
12.1. Throughput of Posted Writes
12.2. Throughput of Non-Posted Reads
13. Design Implementation
13.1. Making Analog QSF Assignments Using the Assignment Editor
13.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins
13.3. Recommended Reset Sequence to Avoid Link Training Issues
13.4. SDC Timing Constraints
14. Additional Features
14.1. Configuration over Protocol (CvP)
14.2. Autonomous Mode
14.2.1. Enabling Autonomous Mode
14.2.2. Enabling CvP Initialization
14.3. ECRC
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14.3.1. ECRC on the TX Path
15. Hard IP Reconfiguration
16. Transceiver PHY IP Reconfiguration
16.1. Connecting the Transceiver Reconfiguration Controller IP Core
16.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
17. Testbench and Design Example
17.1. Endpoint Testbench
17.1.1. Endpoint Testbench for SR-IOV
17.2. Root Port Testbench
17.3. Test Driver Module
17.4. Root Port Design Example
17.5. Root Port BFM Overview
17.5.1. BFM Memory Map
17.5.2. Configuration Space Bus and Device Numbering
17.5.3. Configuration of Root Port and Endpoint
17.5.4. Issuing Read and Write Transactions to the Application Layer
17.6. BFM Procedures and Functions
17.6.1. ebfm_barwr Procedure
17.6.2. ebfm_barwr_imm Procedure
17.6.3. ebfm_barrd_wait Procedure
17.6.4. ebfm_barrd_nowt Procedure
17.6.5. ebfm_cfgwr_imm_wait Procedure
17.6.6. ebfm_cfgwr_imm_nowt Procedure
17.6.7. ebfm_cfgrd_wait Procedure
17.6.8. ebfm_cfgrd_nowt Procedure
17.6.9. BFM Configuration Procedures
17.6.9.1. ebfm_cfg_rp_ep Procedure
17.6.9.2. ebfm_cfg_decode_bar Procedure
17.6.10. BFM Shared Memory Access Procedures
17.6.10.1. Shared Memory Constants
17.6.10.2. shmem_write Task
17.6.10.3. shmem_read Function
17.6.10.4. shmem_display Verilog HDL Function
17.6.10.5. shmem_fill Procedure
17.6.10.6. shmem_chk_ok Function
17.6.11. BFM Log and Message Procedures
17.6.11.1. ebfm_display Verilog HDL Function
17.6.11.2. ebfm_log_stop_sim Verilog HDL Function
17.6.11.3. ebfm_log_set_suppressed_msg_mask Task
17.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task
17.6.11.5. ebfm_log_open Verilog HDL Function
17.6.11.6. ebfm_log_close Verilog HDL Function
17.6.12. Verilog HDL Formatting Functions
17.6.12.1. himage1
17.6.12.2. himage2
17.6.12.3. himage4
17.6.12.4. himage8
17.6.12.5. himage16
17.6.12.6. dimage1
17.6.12.7. dimage2
17.6.12.8. dimage3
17.6.12.9. dimage4
17.6.12.10. dimage5
17.6.12.11. dimage6
17.6.12.12. dimage7
17.7. Setting Up Simulation
17.7.1. Changing Between Serial and PIPE Simulation
17.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
17.7.3. Viewing the Important PIPE Interface Signals
17.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
17.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
17.7.6. Changing between the Hard and Soft Reset Controller
18. Debugging
18.1. Hardware Bring-Up Issues
18.2. Link Training
18.2.1. Debugging Link that Fails To Reach L0
18.2.2. Link Hangs in L0 State
18.3. Use Third-Party PCIe Analyzer
18.4. BIOS Enumeration Issues
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History
C.1. Document Revision History Stratix V Avalon -ST Interface for PCIe Solutions User Guide

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