AN 778: Intel Stratix 10 L-Tile/H-Tile Transceiver Usage - Stratix 10 devices support a transceiver tile architecture. A tile consists of 24 transceiver channels and associated phase locked loops (PLLs), reference clock buffers, and hard IPs. This application note applies to L-tile and H-tile production devices only. - 2022-06-24

Product Type

Device Families > Stratix Families

Device Families > Stratix Families > Stratix 10

Resource Type

Documentation > Application Notes

Source Name

DITA