This chapter provides Hardware Description Language (HDL) coding
style recommendations to ensure optimal synthesis results when targeting Altera FPGA devices.
HDL coding styles have a significant effect on the quality of results for programmable logic designs. Synthesis tools optimize HDL code for both logic utilization and performance; however, synthesis tools cannot interpret the intent of your design. Therefore, the most effective optimizations require conformance to recommended coding styles.
Note: For style recommendations, options, or HDL
attributes specific to your synthesis tool, refer to the synthesis tool vendor’s
documentation.