AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices - Describes the usage and test methodology for the enhanced error detection redundancy check (CRC) feature of the Arria II, Stratix III, Stratix IV, Arria V , Cyclone V , and Stratix V devices. - 2019-08-09
Product Type
Device Families > Arria Families > Arria II
Device Families > Cyclone Families > Cyclone III
Device Families > Cyclone Families
Device Families > Stratix Families > Stratix III
Device Families > Arria Families
Device Families > Stratix Families > Stratix IV
Device Families > Stratix Families
Device Families > Cyclone Families > Cyclone V
Device Families > Stratix Families > Stratix V
Device Families > Arria Families > Arria V
Resource Type
Documentation > Application Notes
Source Name
DITA
1. Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices
1.1. Functional Description
1.1.1. Configuration Error Detection
1.1.2. User Mode Error Detection
1.1.3. Error Detection Pin
1.1.4. Error Message Register
1.1.4.1. EMR for Arria II, Stratix III, and Stratix IV Devices
1.1.4.2. EMR for Arria V, Cyclone V, and Stratix V Devices
1.1.5. Error Detection Timing
1.2. Error Correction
1.3. Using the Error Detection CRC Feature
1.3.1. Error Detection using User Logic
1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal
1.3.1.2. Unloading the EMR through User Logic
1.3.1.3. Accessing the Error Detection Block through User Logic
1.3.1.4. User Logic Control Block
1.3.1.5. User Logic Control Block Signals
1.3.2. Error Detection using an External Host
1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal
1.3.2.2. Unloading the EMR using an External Host
1.4. Error Injection
1.4.1. Fault Injection Register
1.4.1.1. Fault Injection for Arria II, Stratix III, and Stratix IV Devices
1.4.1.2. Fault Injection for Arria V, Cyclone V, and Stratix V Devices
1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction
1.4.2.1. Injecting Single-Bit Error for Arria II, Stratix III, and Stratix IV
1.4.2.2. Injecting Single-Bit Error for Arria V, Stratix V, and Cyclone V Devices
1.4.3. Clearing Fault Injection Register
1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain
1.6. Running .jam Files with the Intel Quartus Prime Jam Tools
1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices